Dell POWEREDGE R710 Series - Speed

Dell™ PowerEdge™ R710 Technical Guidebook
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 •OnechannelperCPUpopulated:
  •ThisisasimpleMemoryOptimizedmode.Mirroringisnotsupported.
The PowerEdge R710 memory interface supports memory demand and patrol scrubbing, single-bit
correction and multi-bit error detection. Correction of a x4 or x8 device failure is also possible with
SDDC in the Advanced ECC mode. Additionally, correction of a x4 device failure is possible in the Memory
Optimized mode. If DIMMs of dierent speeds are mixed, all channels will operate at the fastest common
frequency. RDIMMs and UDIMMs cannot be mixed.
 •Ifmemorymirroringisenabled,identicalDIMMsmustbeinstalledinthesameslotsacrossboth
channels.
 •Thethirdchannelofeachprocessorisunavailableformemorymirroring.
 •TherstDIMMslotineachchanneliscolor-codedwithwhiteejectiontabsforeaseof
installation.
 •TheDIMMsocketsareplaced450mils(11.43mm)apart,center-to-centerinordertoprovide
enough space for sucient airflow to cool stacked DIMMs.
 •ThePER710memorysystemsupportsupto18DIMMs.DIMMsmustbeinstalledineachchannel
starting with the DIMM farthest from the processor. Population order will be identified by the
silkscreen designator and the System Information Label (SIL) located on the chassis cover.
  •MemoryOptimized:{1,2,3},{4,5,6},{7,8,9}
  •AdvancedECCorMirrored:{2,3},{5,6},{8,9}
  •QuadRankorUDIMM:{1,2,3},{4,5,6},{7,8,9}
C. Speed
Memory Speed Limitations
The memory frequency is determined by a variety of inputs:
 •SpeedoftheDIMMs
 •SpeedsupportedbytheCPU
 •CongurationoftheDIMMs