Denon AVC-4310 - Firmware Error Code Reference (Continued); Error Code List (Continued)

22
AVR-4310CI/AVR-4310/AVC-4310
50
Log-in to DPMS has failed when
rewriting firmware such as Sub
CPU, DSP, FPGA, and PLD.
Carry out the update in an environment
that has little network load.
51
Line, etc., is busy when logging
into DPMS when rewriting firm-
ware such as Sub CPU, DSP,
FPGA, and PLD.
Carry out the update in an environment
that has little network load.
52
Connection to DPMS failed when
rewriting firmware such as Sub
CPU, DSP, FPGA, and PLD.
Check the network connection.
Carry out the update in an environment
that has little network load.
53
Connection to DPMS timed out
when rewriting firmware such as
Sub CPU, DSP, FPGA, and PLD.
Check the network connection.
Carry out the update in an environment
that has little network load.
54
Error message received regarding
firmware data after logging in to
DPMS when rewriting firmware
such as Sub CPU, DSP, FPGA,
and PLD.
Turn the power off then back on.
Updating starts automatically.
Carry out the update in an environment
that has little network load.
55
When rewriting firmware such as
Sub CPU, DSP, FPGA, and PLD,
request was made for firmware
data after logging in to DPMS, but
it timed out.
Turn the power off then back on.
Updating starts automatically.
Carry out the update in an environment
that has little network load.
56
Failure to download firmware after
logging in to DPMS when rewriting
firmware such as Sub CPU, DSP,
FPGA, and PLD.
Turn the power off then back on.
Updating starts automatically.
Carry out the update in an environment
that has little network load.
57
Firmware download error received
(line congestion) after logging in to
DPMS when rewriting firmware
such as Sub CPU, DSP, FPGA,
and PLD.
Turn the power off then back on.
Updating starts automatically.
Carry out the update in an environment
that has little network load.
58
Firmware download error received
(connection failure) after logging in
to DPMS when rewriting firmware
such as Sub CPU, DSP, FPGA,
and PLD.
Turn the power off then back on.
Updating starts automatically.
Carry out the update in an environment
that has little network load.
59
When rewriting firmware such as
Sub CPU, DSP, FPGA, and PLD,
request was made for downloading
firmware after logging in to DPMS,
but it timed out.
Turn the power off then back on.
Updating starts automatically.
Carry out the update in an environment
that has little network load.
5A
NACK received when “C” com-
mand sent to Sub CPU, DSP,
FPGA, PLD etc.
Turn the power off then back on.
Updating starts automatically.
5B
NACK received when “L” com-
mand sent to Sub CPU, DSP,
FPGA, PLD etc.
Turn the power off then back on.
Updating starts automatically.
5C
Sub CPU, DSP, FPGA, PLD etc.
failed to receive firmware for
rewriting sent from DM860 (when
timed out).
Turn the power off then back on.
Updating starts automatically.
5D
Sub CPU, DSP, FPGA, PLD etc.
failed to receive firmware for
rewriting sent from DM860 (when
an error).
Turn the power off then back on.
Updating starts automatically.
5E
Invalid data in firmware such as
Sub CPU, DSP, FPGA, and PLD
for rewriting sent from DM860
(when a Check Sum error).
Turn the power off then back on.
Upda
ting st
arts automatically.
Error
code
Details of Error code Display Coping strategies
S
ub
***
mi n
L
og i n f a i l ed 50
S
ub
***
mi n
S
erver is busy51
S
ub
***
mi n
C
onnec t i onFa i l 52
S
ub
***
mi n
C
onnec t i onFa i l 53
S
ub
***
mi n
U
pda t i ng f a i l 54
S
ub
***
mi n
U
pda t i ng f a i l 55
S
ub
***
mi n
D
own l oad f a i l 56
S
ub
***
mi n
S
erver is busy57
S
ub
***
mi n
C
onnec t i onFa i l 58
S
ub
***
mi n
D
own l oad f a i l 59
S
ub
***
mi n
C
onnec t i onFa i l 5A
S
ub
***
mi n
U
pda t i ng f a i l 5B
S
ub
***
mi n
U
pda t i ng f a i l 5C
S
ub
***
mi n
U
pda t i ng f a i l 5D
S
ub
***
mi n
U
pda t i ng f a i l 5E