Denon D-E500 - Page 38

38
RCD-M37 / RCD-M37DAB / D-E500 / D-M37
Pin
No.
Symbol I/O Description Default Remarks
56
IPF
O
3I/F
Correction flag output O CMOS PORT
57
SFSY
O
3I/F
Servo internal register read clock output pin O CMOS PORT
58
ZDET
O
3I/F
Internal Audio DAC Zero data detection flag
output
O CMOS PORT
59
GPIN
I
3I/F
CD General Input port(Pull down by 100K:
when not in use)
I Schmitt input
60
MS
I
3I/F
Microprocessor I/F mode selection pin.
“H”: Parallel I/F, “L”: Serial I/F
I
61
DoUT(Po6)
O
3I/F
Digital Audio output (SPDIF) pin
(DSP general output port -6)
O CMOS PORT
62
AoUT1(Po7)
O
3I/F
Audio data output pin -1(DSP general
output port -7)
O CMOS PORT
63
BCKo(Po8)
O
3I/F
Bit clock output pin for AoUT
(DSP general output port -8)
O CMOS PORT
64
LRCKo(Po9)
O
3I/F
L/R channel clock output pin
(DSP general output port -9)
O CMOS PORT
65
AiN(Pi4)
I
3I/F
Audio data input for Audio DAC
(DSP general input port -4)
I Schmitt input
66
BCKi(Pi5)
I
3I/F
Bit clock input pin for AiN
(DSP general input port -5)
I Schmitt input
67
LRCKi(Pi6)
I
3I/F
L/R channel clock for AiN
(DSP general input port -6)
I Schmitt input
68
VDD1
㧙
Power supply pin for 1.5V digital circuit.
㧙
69
VSS
㧙
Grounding pin for 1.5V digital circuit.
㧙
70
AWRC
O
3AI/F
VCO control pin for active wide-range PLL O
Applicable in CLV/CAV
mode. Connect 0.033 uF.
71
PVDD3
㧙
Power supply pin for 3.3V CD PLL circuit.
㧙
72
PDo
O
3AI/F
EFM and PLCK Phase difference signal
output pin.
O
4-state output (
PVDD3,
Hiz,PVSS3,PVREF)
73
TMAXS
O
3AI/F
TMAX detection result output pin O
3-state output
(PVDD3,PVSS3,HiZ)
74
TMAX
O
3AI/F
TMAX detection result output pin O
3-state
output(PVDD3,PVSS3,HiZ)
75
LPFN
I
3AI/F
PLL circuit LPF amplifier inversion input pin I
Connect resister of LPF,
refer to application circuit
diagram.
76
LPFo
O
3AI/F
PLL circuit LPF amplifier Output pin O
Connect capacitor of LPF,
refer to application circuit
diagram.
77
PVREF
㧙
PLL circuit 1.65 V reference voltage pin.
㧙
Connected to VREF and
VRO inside of IC. Connect
0.1uF.
78
VCoF
O
3AI/F
VCO filter pin O Connect 0.01uF.
79
PVSS3
㧙
Grounding pin for 3.3V CD PLL circuit.
㧙
80
SLCo
O
3AI/F
EFM slice level output pin.
Output impedance =2.5kǡ both of
analog/digital slice mode.
O
Connect capacitor
according with servo
frequency band.
81
RFi
I
3AI/F
RF signal input pin
Zin is selectable by command.
I
Zin㧦20kǡ㧘10kǡ㧘5kǡ
82
RFRPi
I
3AI/F
RF ripple signal input pin I