Denon DCD-315 - Page 21

a gE I EEE EES OS-315 Sa
DA14 output at PSSL=1, 64 bit slot serial data at PSSL=0.
DA13 output at PSSL=1, 64 bit slot bit clock at PSSL=0.
DAO8 output at PSSL=1, GFS output at PSSL=0.
DAO3 output at PSSL=1, MNT2 output at PSSL=0.
DAO2 output at PSSL=1, MNT1 output at PSSL=0.
DAO1 output at PSSL=1, MNTO output at PSSL=0.
X'tal Osc, circuit input.
| __Symbol__|
DVppb
ASYE
PSSL
WDCK
LRCK
DATA
BCLK
64DAT.
64BCLK
64LRC!
GTOP
XUGF
XPLCK
GFS
RFCK
C2PO
XRAOF
MNT3
MNT2
MNT1
MNTO
XTAI
XTAO
XTSL
DVss
FSTI
FSTO
C4M
C16M
42
43
44
5
bh
47
48
A
5 =
57
fo») =
N
Digital-Out output terminal.
Sub code sync output terminal.
Sub P~W serial output.
[SENS output. SSCS
lock for SENS serial data read out.
X’tal Osc, circuit output
67
71
72
7
DOUT
EMPH
WECK
SCOR
N
@
4
76
77
78
9
EXCK
SUBQ
SQCK
MUTE
™N
oo
1 XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
fo)
OD
iS}
3 Cc
4
Seria! data transfer clock input from CPU.
o
87
8
fos)
21