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8 BENCH TESTING MODULES
The following methods have been devised to permit the user to perform simple module tests
on the bench and confirm basic input to output operation. Field units that do not perform as
described below, or modules that have ‘unusual’ operating behaviour, should be replaced and
returned to Eaton.
Consult individual module wiring diagrams for terminal connections.
Unless stated specifically, the module will require dc power, as if under normal
operating conditions.
8.1 Digital Input (DI) modules
8.1.1 Modules:
MTL 5501-SR, MTL5510, MTL5510B, MTL5511, MTL5513, MTL5514(-T),
MTL5514D, MTL5516C, MTL5517
Input Conditions
1. Connect the appropriate input test circuit to the channel under test (see Figure 8.1 &
Table 8.1).
2. For multi-channel modules with LFD, connect a 22kΩ resistor across the other channel
input(s) to prevent the signalling of an unwanted open-circuit line fault.
3. Where appropriate test with phase reversal switch in both OFF and ON conditions.
Model Resistor values Switch – simulation conditions
MTL5501-SR R
1
= 10kΩ, R
2
= 1k4Ω
a) Normal - field switch open
b) Normal - field switch closed
c) Line Fault - Test for short circuit
d) Line Fault - Test for open circuit
MTL5510/5510B
MTL5511
MTL5513
MTL5514/5514D
MTL5516C
MTL5517
R
1
= 22kΩ, R
2
= 680Ω
Output Results
1. For MTL5510 and MTL5510B modules refer to pages 13-15 of this manual.
2. The phase reversal switch will reverse the channel output conditions, but not the LFD.
3. With LFD disabled (OFF) the Status LED should respond as shown in Table 8.2.
4. With LFD disabled (ON) the LEDs and relay should respond as shown in Table 8.3.
Input switch
positions
Channel contacts
Status
LED
NC NO
a Closed Open OFF
b Open Closed ON
c Open Closed ON
d Closed Open OFF
Input switch
positions
Channel contacts LEDs LFD relay
NC NO Status LFD MTL550x MTL551x
a Closed Open OFF OFF
Energised De-energised
b Open Closed ON OFF
Energised De-energised
c Closed Open OFF ON
De-energised Energised
d Closed Open OFF ON
De-energised Energised
Figure 8.1:
DI input
test circuit
Table 8.1:
Input test
conditions
Table 8.2:
Output test
results