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Using BIOS
DRAM Configuration
Scroll to this item and press <Enter> to view the following screen:
(Press Enter)
Timing Mode [Auto]
Item Help
Menu Level
Phoenix-AwardBIOS CMOS Setup Utility
DRAM Configuration
x
Memclock index value or Limi DDR2 400
SPD Checksum Restart [Ignore]
DCTs mode [Ganged]
CKE base power down mode [Disabled]
CKE based powerdown [Per channel]
Memclock tri-string [Disabled]
Memory Hole Remapping [Enabled]
Auto Optimize Bottom IO [Enabled]
Bottom of [31:24] IO space E0
x
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
Timing Mode (Auto)
This item allows you to set up the DRAM timing nanually or automatically.
Memory Clock value or Limi (DDR2 400)
When DDR2 Timing Setting by is set to Manual, use this item to set the DRAM
frequency.
CKE base power down mode (Enabled)
When in power down mode, if all pages of the DRAMs associated with a CKE pin
are closed, then these parts are placed in power down mode. Only pre-charge power
down mode is supported, not active power down mode.
SPD Checksum Restart (Ignore)
DCTs mode (Ganged)
This item is used to select the DCTs mode (DRAM Controllers mode). when set to
Ganged, it will behave as a single dual channel DCT; when set to Unganged, it will
behave as two single channel DCTs.
This item enables or disables SPD Checksum Restart function. when set to exit, it will
exit current node initialization if there is any DIMM SPD checksum error; when set
to ignore, it will ignore the faulty SPD checksums.
CKE based powerdown (Per Channel)
The DRAM channel is placed in power down when all chip selects associated with
the channel are idle.
Memclock tri-stating (Disabled)
This item enables or disables memclock tri-stating function.
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