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Using BIOS
Timing Mode (Auto)
This item allows you to set up the DRAM timing nanually or automatically.
Memclock index value (Mhz) (200MHz)
When DDR Timing Setting by is set to Manual, use this item to set the DRAM frequency.
LDT & PCI Bus Control (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
LDT Configuration (Enabled)
This item enables or disables the LDT configuration.
LDT Configuration [Enabled]
Upstream LDT Bus Width [16 bit]
Downstream LDT Bus Width [16 bit]
LDT Bus Frequency [Auto]
PCIE Reset Delay [Disabled]
Item Help
Menu Level
Phoenix-AwardBIOS CMOS Setup Utility
Advanced Chipset Features
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
CAS# latency (Tcl) (2.5)
This item determines the operation of SDRAM memory CAS (column address strobe). It
is recommended that you leave this item at the default value. The 2T setting requires
faster memory that specifically supports this mode.
Press <Esc> to return to the Advanced Chipset Features page.
Upstream LDT Bus Width (16 bit)
This item allows users to manually adjust the upstream LDT bus width to be 8 bit or 16
bit.
Downstream LDT Bus Width (16 bit)
This item allows users to manually adjust the downstream LDT bus width to be 8 bit or
16 bit.
PCIE Reset Delay (Disabled)
This item enables or disables the PCIE reset delay.
Press <Esc> to return to the Advanced Chipset Features page.
UMA Frame Buffer Size [32MB]
This item allows users to manually adjust the UMA frame buffer size, from 16MB to
128MB.
LDT Bus Frequency (Auto)
This item allows users to manually adjust the LDT Bus Frequency.
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