Espressif Systems ESP32-C3 Series - RTC Clock (Optional)

2 Schematic Checklist
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NC: No component.
The values of C8, L2 and C9
vary with the actual PCB board.
The values of C1 and C2 vary with
the selection of the crystal.
The value of R1 varies with the actual
PCB board.
If using ESP32-C3FN4 or ESP32-C3FH4,
flash is not mounted.
GPIO19
CHIP_EN
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
U0RXD
GPIO18
LNA_IN
GPIO9
GPIO10
GPIO0
GPIO1
SPICS0
SPID
SPIQ
SPICLK
SPIWP
SPIHDGPIO2
GPIO3
RF_ANT
U0TXD
SPICLK
SPICS0
SPIHD SPIWP
SPID
SPIQ
XTAL_P
GND
VDD33
GND
GND
GNDGND GND
GND GND
GND
VDD33
GND GNDGND
VDD33
VDD_SPI
VDD33
GND
VDD_SPI
GND
GND
GND GND
GND
VDD33
GND
C1
TBD
C9
TBD
R4 0
U3 FLASH-3V3
/CS
1
DO
2
/WP
3
GND
4
DI
5
CLK
6
/HOLD
7
VCC
8
L3
TBD
R7 0
R6 0
ANT1
PCB_ANT
1
2
R1 0
C12
0.1uF
C3
1uF
C10
0.1uF
R5 0
R1 0
R3 0
R2 499
C1
10nF
C8
TBD
C2
TBD
L1 2.0nH
C6
0.1uF
Y1
40MHz(±10ppm)
VCC
4
NC
1
GND
2
OUT
3
C5
10uF
L2
TBD
C7
1uF
C4
10nF
U2 ESP32-C3
LNA_IN
1
VDD3P3
2
VDD3P3
3
XTAL_32K_P
4
XTAL_32K_N
5
GPIO2
6
CHIP_EN
7
MTMS
9
MTDI
10
VDD3P3_RTC
11
MTCK
12
MTDO
13
GPIO8
14
GPIO9
15
GPIO10
16
VDD3P3_CPU
17
VDD_SPI
18
SPIHD
19
SPIWP
20
SPICS0
21
SPICLK
22
SPID
23
SPIQ
24
U0RXD
27
U0TXD
28
XTAL_N
29
XTAL_P
30
GND
33
GPIO3
8
VDDA
32
VDDA
31
GPIO19
26
GPIO18
25
C11
1uF
R8
10K
U1
40MHz(±10ppm)
XIN
1
GND
2
XOUT
3
GND
4
Figure 7: Schematic for ESP32C3 Family’s Oscillator
Notice:
• If you use an oscillator, its output should be connected to XTAL_P on the chip through a series inductor
(initially of 20 nH). XTAL_N can be floating. Please make sure that the oscillator output is stable and
its accuracy is within ±10 ppm. It is also recommended that the circuit design for the oscillator is
compatible with the use of crystal, in case that if there is a problem with oscillator circuit, the oscillator
can be replaced by the crystal.
• Although ESP32-C3 family has calibration circuits, defects in the crystal itself (for example, large fre-
quency deviation of more than ±10 ppm, unstable performance over operating temperature range, etc)
may lead to the malfunction of ESP32-C3 family, resulting in RF performance degradation.
2.4.2 RTC Clock (optional)
ESP32-C3 family supports an external 32.768 kHz crystal to act as the RTC sleep clock.
Figure 8 shows the schematic for the external 32.768 kHz crystal.
Figure 8: Schematic for ESP32C3 Family’s External Crystal (RTC)
Notice:
• Requirements for the 32.768 kHz crystal:
– Equivalent series resistance (ESR) ⩽ 70 kΩ.
– Load capacitance at both ends should be configured according to the crystal’s specification.
• The parallel resistor R10 is used for biasing the crystal circuit (5 MΩ < R12 ⩽ 10 MΩ). In general, you
do not need to populate R10.
• If the RTC source is not required, then pin 4 (XTAL_32K_P) and pin 5 (XTAL_32K_N) can be used as
general GPIOs.
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ESP32-C3 Family Hardware Design Guidelines V0.5