Espressif Systems ESP32-C3 Series - Flash Memory SPI Layout; UART Signal Integrity Layout

3 PCB Layout Design
0.33
4
4
0.4
0.4
0.8
0.8
4.39
4.43
4.39
Core
1
1
0.33
Stack up
Core
PP
L1_Top
L2_Gnd
L3_Power
PP
L4_Bottom
SM
SM
1.2
8
8
1.2
Material
Base copper
(oz)
Finshed Copper 1 oz
7628 TG150 RC50%
7628 TG150 RC50%
Finshed Copper 1 oz
Adjustable
Thickness
(mil)
DK
Gap (mil) Gap (mil) Width (mil) Impedance (Ohm) Thickness (mm)
12.2 12.6 12.2 - 50
0.33
4
4
0.4
0.4
0.8
0.8
4.39
4.43
4.39
о°å
1
1
0.33
µþ²ã
Core
PP
L1_Top
L2_Gnd
L3_Power
PP
L4_Bottom
×躸²ã
1.2
8
8
1.2
²ÄÖÊ »ùÍ-ºñ (oz)
³ÉÆ·Í-ºñ 1 oz
7628 TG150 RC50%
7628 TG150 RC50%
¿Éµ÷
ºñ¶È (mil) ½éµç³£Êý
³ÉÆ·Í-ºñ 1 oz
×迹 (Ohm) ºñ¶È (mm)
- 50
Ïß¿í (mil)Í-¾à (mil)
12.2 12.6 12.2
Í-¾à (mil)
×躸²ã
Figure 20: ESP32C3 Family PCB Stackup Design
3.6 Flash
Place the reserved serial resistor on the SPI interface close to the chip side. Route the SPI traces on the inner
layer (e.g., the third layer) whenever possible. Add ground copper and ground vias around the clock and data
traces of SPI separately.
Figure 21: ESP32C3 Family Flash Layout
3.7 UART
The series resistor on the U0TXD line needs to be placed close to the chip and away from the crystal. The
U0TXD and U0RXD traces on the top layer should be as short as possible, surrounded by ground copper and
ground vias.
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ESP32-C3 Family Hardware Design Guidelines V0.5