2 Schematic Checklist
2.5 RF
In your circuit design, please add a π-matching network for antenna matching, preferably a CLC network.
NC: No component.
The values of C8, L2 and C9
vary with the actual PCB board.
The values of C1 and C2 vary with
the selection of the crystal.
The value of R1 varies with the actual
PCB board.
GPIO19
CHIP_EN
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
U0RXD
GPIO18
LNA_IN
GPIO9
GPIO10
GPIO0
GPIO1
SPICS0
SPID
SPIQ
SPICLK
SPIWP
SPIHDGPIO2
GPIO3
RF_ANT
U0TXD
SPICLK
SPICS0
SPIHD SPIWP
SPID
SPIQ
GND
VDD33
GND
GND
GNDGND GND
GND GND
GND
VDD33
GND GNDGND
VDD33
VDD_SPI
VDD33
GND
VDD_SPI
GND
GND
GND GND
C1
TBD
C9
TBD
U3 FLASH-3V3
/CS
1
DO
2
/WP
3
GND
4
DI
5
CLK
6
/HOLD
7
VCC
8
R4 0
R7 0
R6 0
C12
0.1uF
R1 0
ANT1
PCB_ANT
1
2
R5 0
C10
0.1uF
C3
1uF
R2 499
R3 0
L1 2.0nH
C2
TBD
C8
TBD
C6
0.1uF
L2
TBD
C5
10uF
C4
100pF
C7
0.1uF
C11
1uF
U2 ESP32-C3
LNA_IN
1
VDD3P3
2
VDD3P3
3
XTAL_32K_P
4
XTAL_32K_N
5
GPIO2
6
CHIP_EN
7
MTMS
9
MTDI
10
VDD3P3_RTC
11
MTCK
12
MTDO
13
GPIO8
14
GPIO9
15
GPIO10
16
VDD3P3_CPU
17
VDD_SPI
18
SPIHD
19
SPIWP
20
SPICS0
21
SPICLK
22
SPID
23
SPIQ
24
U0RXD
27
U0TXD
28
XTAL_N
29
XTAL_P
30
GND
33
GPIO3
8
VDDA
32
VDDA
31
GPIO19
26
GPIO18
25
U1
40MHz(±10ppm)
XIN
1
GND
2
XOUT
3
GND
4
R8
10K
Figure 9: ESP32C3 Family RF Matching Schematic
Note:
The parameters of the components in the matching network are subject to the actual antenna and PCB layout.
2.6 UART
You need to connect a 499 Ω resistor to the U0TXD line to suppress the 80 MHz harmonics.
2.7 ADC
It is recommended to add a 0.1 µF filter capacitor between pins and ground when using the ADC function. ADC1
is more preferable.
2.8 Strapping Pins
Note:
The content below is excerpted from Section Strapping Pins in ESP32-C3 Family Datasheet.
ESP32-C3 family has three strapping pins:
• GPIO2
• GPIO8
• GPIO9
• GPIO10
Espressif Systems 11
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ESP32-C3 Family Hardware Design Guidelines V0.5
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