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The central core of ARM Cortex-M3 processor, based on a 3-stage pipeline
Harvard bus architecture, incorporates advanced features including single cycle
multiply and hardware divide to deliver an outstanding efficiency of 1.25
DMIPS/MHz. The ARM Cortex-M3 processor also implements the new Thumb®-2
instruction set architecture, which combined with features such as unaligned data
storage and atomic bit manipulation delivers 32-bit performance at a cost equivalent to
modern 8- and 16-bit devices.
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