Fluke 8024B - Page 52

8024B
3-7.
The
digital
control
portion
of
the
a/d
converter
process
is
an
internal
function
of
U8,
and
is
keyed
to
the
external
crystal
frequency.
As
a
result,
the
conversion
process
iS
continuously
repeated,
and
the
display
is
updated
at
the
end
of
every
conversion
cycle.
3-8.
A
simplified
circuit
diagram
of
the
analog
portion
of
the
a/d
converter
is
shown
in
Figure
3-2.
Each
of
the
switches
shown
represent
analog
gates
which
are
operated
by
the
digital
section
of
the
a/d
converter.
(Sheet
|
of
the
Schematic
also
illustrates
the
a/d
converter
in
a
block
form.)
Basic
timing
for
switch
operation
and,
therefore,
a
complete
measurement
cycle
is
shown
in
Figure
3-3.
3-9,
Any
given
measurement
cycle
performed
by
the
a/d
converter
can
be
divided
into
three
consecutive
time
periods,
autozero
(AZ),
integrate
(INTEG),
and
read.
Both
autozero
and
integrate
are
fixed
time
periods
whose
lengths
are
multiples
of
the
clock
frequency.
A
counter
determines
the
length
of
both
time
periods
by
providing
an
overflow
at
the
end
of
every
10,000
clock
pulses.
The
read
period
is
a
variable
time
which
is
proportional
to
the
unknown
input
voltage.
The
value
of
the
voltage
is
determined
by
counting
the
number
of
clock
pulses
that
occur
during
the
read
period.
3-10.
During
autozero,
a
ground
reference
is
applied
as
an
input
to
the
a/d
converter.
Under
ideal
conditions
the
output
of
the
comparator
would
also
go
to
zero.
However,
input-offset-voltage
errors
accumulate
in
the
amplifier
loop,
and
appear
at
the
comparator
output
as
an
error
voltage.
This
error
is
impressed
across
the
AZ
capacitor
where
it
is
stored
for
the
remainder
of
the
measurement
cycle.
The
stored
level
is
used
to
provide
offset
voltage
correction
during
the
integrate
and
read
periods.
3-11,
The
integrate
period
begins
at
the
end
of
the
autozero
period.
As
the
period
begins,
the
AZ
switch
opens
and
the
INTEG
switch
closes.
This
applies
the
unknown
input
voltage
to
the
input
of
the
a/d
converter.
The
voltage
is
buffered
and
passed
on
to
the
integrator
to
determine
the
charge
rate
(slope)
on
the
INTEG
capacitor.
At
the
end
of
the
fixed
integrate
period,
the
capacitor
is
charged
to
a
level
proportional
to
the
unknown
input
voltage.
This
voltage
is
translated
to
a
digital
indication
by
discharging
the
capacitor
at
a
fixed
rate
during
the
read
period,
and
counting
the
number
of
clock
pulses
that
occur
before
it
returns
to
the
original
autozero
level.
3-12.
As
the
read
period
begins,
the
INTEG
switch
opens
and
the
read
switch
closes.
This
applies
a
known
reference
voltage
to
the
input
of
the
a/d
converter.
The
polarity
of
this
voltage
is
automatically
selected
to
be
opposite
that
of
the
unknown
input
voltage,
thus
causing
the
INTEG
capacitor
to
discharge
at
a
fixed
rate
(slope).
When
the
charge
is
equal
to
the
initial
starting
point
(autozero
level),
the
read
period
is
ended.
Since
the
discharge
slope
is
fixed
during
the
read
period,
the
time
required
for
discharge
is
proportional
to
the
unknown
input
voltage.
3-13.
The
autozero
period,
and
thus
a
new
measurement
cycle,
begins
at
the
end
of
the
read
period.
At
the
same
time
the
counter
is
released
for
operation
by
transferring
its
contents
(previous
measurement
value)
to
a
series
of
latches.
This
stored
data
is
then
decoded
and
buffered
before
being
used
for
driving
the
liquid
crystal
display.
3-3