Freescale Semiconductor MC9S12XE Series

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HCS12X

Microcontrollers

freescale.com

MC9S12XEP100

Reference Manual

Covers MC9S12XE Family

MC9S12XEP100RMV1

Rev. 1.19

12/2008

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages

Main Page

Chapter 1 Device Overview MC9S12XE-Family27
- 1.1 Introduction27
- 1.2 Signal Description42
- 1.3 System Clock Description75
- 1.4 Modes of Operation76
- 1.5 Security80
- 1.6 Resets and Interrupts80
- 1.7 ADC0 Configuration86
  - 1.7.1 External Trigger Input Connection86
  - 1.7.2 ADC0 Channel[17] Connection86
- 1.8 ADC1 External Trigger Input Connection86
- 1.9 MPU Configuration87
- 1.10 VREG Configuration87
  - 1.10.1 Temperature Sensor Configuration87
- 1.11 S12XEPIM Configuration87
- 1.12 Oscillator Configuration88
Chapter 2 Port Integration Module (S12XEP100PIMV1)89
- 2.1 Introduction89
  - 2.1.1 Overview89
  - 2.1.2 Features90
- 2.2 External Signal Description90
- 2.3 Memory Map and Register Definition98
- 2.4 Functional Description178
- 2.5 Initialization Information186
  - 2.5.1 Port Data and Data Direction Register writes186
Chapter 3 Memory Mapping Control (S12XMMCV4)187
- 3.1 Introduction187
- 3.2 External Signal Description190
- 3.3 Memory Map and Registers192
  - 3.3.1 Module Memory Map192
  - 3.3.2 Register Descriptions193
- 3.4 Functional Description204
- 3.5 Initialization/Application Information218
Chapter 4 Memory Protection Unit (S12XMPUV1)227
- 4.1 Introduction227
- 4.2 External Signal Description229
- 4.3 Memory Map and Register Definition229
  - 4.3.1 Register Descriptions230
- 4.4 Functional Description237
  - 4.4.1 Protection Descriptors237
  - 4.4.2 Interrupts239
    - 4.4.2.1 Description of Interrupt Operation239
    - 4.4.2.2 CPU Access Error Interrupt239
- 4.5 Initialization/Application Information239
  - 4.5.1 Initialization239
Chapter 5 External Bus Interface (S12XEBIV4)241
- 5.1 Introduction241
- 5.2 External Signal Description243
- 5.3 Memory Map and Register Definition245
  - 5.3.1 Module Memory Map245
  - 5.3.2 Register Descriptions245
    - 5.3.2.1 External Bus Interface Control Register 0 (EBICTL0)245
    - 5.3.2.2 External Bus Interface Control Register 1 (EBICTL1)247
- 5.4 Functional Description248
- 5.5 Initialization/Application Information256
  - 5.5.1 Normal Expanded Mode256
    - 5.5.1.1 Example 1a: External Wait Feature Disabled257
    - 5.5.1.2 Example 1b: External Wait Feature Enabled257
  - 5.5.2 Emulation Modes257
    - 5.5.2.1 Example 2a: Emulation Single-Chip Mode258
    - 5.5.2.2 Example 2b: Emulation Expanded Mode259
Chapter 6 Interrupt (S12XINTV2)261
- 6.1 Introduction261
- 6.2 External Signal Description264
- 6.3 Memory Map and Register Definition265
  - 6.3.1 Module Memory Map265
  - 6.3.2 Register Descriptions266
- 6.4 Functional Description271
- 6.5 Initialization/Application Information275
Chapter 7 Background Debug Module (S12XBDMV2)277
- 7.1 Introduction277
- 7.2 External Signal Description279
- 7.3 Memory Map and Register Definition280
- 7.4 Functional Description285
Chapter 8 S12X Debug (S12XDBGV3) Module303
- 8.1 Introduction303
- 8.2 External Signal Description306
- 8.3 Memory Map and Registers306
  - 8.3.1 Module Memory Map306
  - 8.3.2 Register Descriptions308
- 8.4 Functional Description324
Chapter 9 Security (S12XE9SECV2)345
- 9.1 Introduction345
Chapter 10 XGATE (S12XGATEV3)351
- 10.1 Introduction351
- 10.2 External Signal Description354
- 10.3 Memory Map and Register Definition354
  - 10.3.1 Register Descriptions354
- 10.4 Functional Description371
- 10.5 Interrupts377
  - 10.5.1 Incoming Interrupt Requests377
  - 10.5.2 Outgoing Interrupt Requests377
- 10.6 Debug Mode377
  - 10.6.1 Debug Features377
    - 10.6.1.0.1 Entering Debug Mode378
  - 10.6.2 Leaving Debug Mode379
- 10.7 Security379
- 10.8 Instruction Set380
- 10.9 Initialization and Application Information461
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)467
- 11.1 Introduction467
- 11.2 Signal Description469
  - 11.2.1 VDDPLL, VSSPLL469
  - 11.2.2 RESET469
- 11.3 Memory Map and Registers470
  - 11.3.1 Module Memory Map470
  - 11.3.2 Register Descriptions471
- 11.4 Functional Description484
- 11.5 Resets492
  - 11.5.1 Description of Reset Operation493
- 11.6 Interrupts495
  - 11.6.1 Description of Interrupt Operation496
Chapter 12 Pierce Oscillator (S12XOSCLCPV2)497
- 12.1 Introduction497
- 12.2 External Signal Description498
  - 12.2.1 VDDPLL and VSSPLL - Operating and Ground Voltage Pins498
  - 12.2.2 EXTAL and XTAL - Input and Output Pins498
- 12.3 Memory Map and Register Definition500
- 12.4 Functional Description500
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)501
- 13.1 Introduction501
- 13.2 Signal Description504
  - 13.2.1 Detailed Signal Descriptions504
- 13.3 Memory Map and Register Definition504
  - 13.3.1 Module Memory Map504
  - 13.3.2 Register Descriptions506
- 13.4 Functional Description521
  - 13.4.1 Analog Sub-Block521
  - 13.4.2 Digital Sub-Block522
    - 13.4.2.1 External Trigger Input522
    - 13.4.2.2 General-Purpose Digital Port Operation523
- 13.5 Resets523
- 13.6 Interrupts523
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)525
- 14.1 Introduction525
- 14.2 External Signal Description526
- 14.3 Memory Map and Register Definition527
  - 14.3.1 Module Memory Map527
  - 14.3.2 Register Descriptions528
- 14.4 Functional Description562
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description577
- 15.1 Introduction577
- 15.2 External Signal Description578
  - 15.2.1 IIC_SCL - Serial Clock Line Pin578
  - 15.2.2 IIC_SDA - Serial Data Line Pin578
- 15.3 Memory Map and Register Definition579
  - 15.3.1 Register Descriptions579
- 15.4 Functional Description591
- 15.5 Resets596
- 15.6 Interrupts596
- 15.7 Application Information597
  - 15.7.1 IIC Programming Examples597
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)603
- 16.1 Introduction603
- 16.2 External Signal Description605
- 16.3 Memory Map and Register Definition606
- 16.4 Functional Description639
- 16.5 Initialization/Application Information656
  - 16.5.1 MSCAN initialization656
  - 16.5.2 Bus-Off Recovery657
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)659
- 17.1 Introduction659
- 17.2 External Signal Description660
- 17.3 Register Definition661
- 17.4 Functional Description671
- 17.5 Initialization674
- 17.6 Application Information674
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)677
- 18.1 Introduction677
- 18.2 External Signal Description678
- 18.3 Register Definition678
- 18.4 Functional Description687
- 18.5 Initialization689
- 18.6 Application Information690
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)691
- 19.1 Introduction691
- 19.2 External Signal Description692
- 19.3 Memory Map and Register Definition693
  - 19.3.1 Module Memory Map693
  - 19.3.2 Register Descriptions694
- 19.4 Functional Description709
  - 19.4.1 PWM Clock Select709
  - 19.4.2 PWM Channel Timers712
- 19.5 Resets720
- 19.6 Interrupts721
Chapter 20 Serial Communication Interface (S12SCIV5)723
- 20.1 Introduction723
- 20.2 External Signal Description725
  - 20.2.1 TXD - Transmit Pin725
  - 20.2.2 RXD - Receive Pin725
- 20.3 Memory Map and Register Definition725
  - 20.3.1 Module Memory Map and Register Definition726
  - 20.3.2 Register Descriptions726
- 20.4 Functional Description737
- 20.5 Initialization/Application Information756
Chapter 21 Serial Peripheral Interface (S12SPIV5)761
- 21.1 Introduction761
- 21.2 External Signal Description763
- 21.3 Memory Map and Register Definition764
  - 21.3.1 Module Memory Map764
  - 21.3.2 Register Descriptions765
- 21.4 Functional Description773
Chapter 22 Timer Module (TIM16B8CV2) Block Description787
- 22.1 Introduction787
- 22.2 External Signal Description791
- 22.3 Memory Map and Register Definition792
  - 22.3.1 Module Memory Map792
  - 22.3.2 Register Descriptions792
- 22.4 Functional Description808
- 22.5 Resets812
- 22.6 Interrupts812
Chapter 23 Voltage Regulator (S12VREGL3V3V1)815
- 23.1 Introduction815
- 23.2 External Signal Description818
- 23.3 Memory Map and Register Definition819
  - 23.3.1 Module Memory Map820
  - 23.3.2 Register Descriptions820
- 23.4 Functional Description826
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)831
- 24.1 Introduction831
- 24.2 External Signal Description835
- 24.3 Memory Map and Registers836
  - 24.3.1 Module Memory Map836
  - 24.3.2 Register Descriptions841
- 24.4 Functional Description862
- 24.5 Security887
- 24.6 Initialization889
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1)891
- 25.1 Introduction892
- 25.2 External Signal Description895
- 25.3 Memory Map and Registers896
  - 25.3.1 Module Memory Map896
  - 25.3.2 Register Descriptions901
- 25.4 Functional Description922
- 25.5 Security950
- 25.6 Initialization952
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1)953
- 26.1 Introduction954
- 26.2 External Signal Description957
- 26.3 Memory Map and Registers958
  - 26.3.1 Module Memory Map958
  - 26.3.2 Register Descriptions963
- 26.4 Functional Description984
- 26.5 Security1012
- 26.6 Initialization1014
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)1015
- 27.1 Introduction1016
- 27.2 External Signal Description1019
- 27.3 Memory Map and Registers1020
  - 27.3.1 Module Memory Map1020
  - 27.3.2 Register Descriptions1025
- 27.4 Functional Description1046
- 27.5 Security1073
- 27.6 Initialization1075
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2)1077
- 28.1 Introduction1078
- 28.2 External Signal Description1081
- 28.3 Memory Map and Registers1082
  - 28.3.1 Module Memory Map1082
  - 28.3.2 Register Descriptions1087
- 28.4 Functional Description1108
- 28.5 Security1135
- 28.6 Initialization1137
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2)1139
- 29.1 Introduction1140
- 29.2 External Signal Description1143
- 29.3 Memory Map and Registers1144
  - 29.3.1 Module Memory Map1144
  - 29.3.2 Register Descriptions1150
- 29.4 Functional Description1171
- 29.5 Security1198
- 29.6 Initialization1200
Appendix A Electrical Characteristics1201
- A.1 General1201
- A.2 ATD Characteristics1219
- A.3 NVM, Flash and Emulated EEPROM1224
  - A.3.1 Timing Parameters1224
  - A.3.2 NVM Reliability Parameters1231
- A.4 Voltage Regulator1233
- A.5 Output Loads1233
- A.6 Reset, Oscillator and PLL1235
- A.7 External Interface Timing1240
Appendix B Package Information1257
- B.1 208 MAPBGA1258
- B.2 144-Pin LQFP1258
- B.3 112-Pin LQFP Package1260
- B.4 80-Pin QFP Package1261
Appendix C PCB Layout Guidelines1262
Appendix D Derivative Differences1267
- D.1 Memory Sizes and Package Options S12XE - Family1267
- D.2 Pinout explanations:1269
Appendix E Detailed Register Address Map1270
Appendix F Ordering Information1321

Brand	Freescale Semiconductor
Model	MC9S12XE Series
Category	Microcontrollers
Language	English

Freescale Semiconductor MC9S12XE Series - User Manual

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