Gigabyte G492-ZD2 - Page 118

BIOS Setup - 118 -
Parameter
Description
PCIe Root Port UnCorr Err
Mask Reg
Initialize the PCIe AER Uncorrected Error Mask register of Root Port.
PCIe Root Port UnCorr Err
Sev Reg
Initialize the PCIe AER Uncorrected Error Severity register of Root Port.
PCIe Device Corr Err Mask
Reg
Initialize the PCIe AER Corrected Error Mask register of PCIe device.
PCIe Device UnCorr Err
Mask Reg
Initialize the PCIe AER Uncorrected Error Mask register of PCIe device.
PCIe Device UnCorr Err Sev
Reg
Initialize the PCIe AER Uncorrected Error Severity register of PCIe
device.
CCIX GHES Deferred ERR
Notify Type
Selects the Notication type for CCIX deferred error.
Options available: Polled, SCI. Default setting is Polled.
CCIX GHES Corrected Err
Notify Type
Selects the Notication type for CCIX corrected error.
Options available: Polled, SCI. Default setting is Polled.
DDR4 DRAM Hard Post
Package Repair
This feature allows spare DRAM rows to replace malfunctioning rows via
an in-eld repair mechanism.
Options available: Enabled, Disabled. Default setting is Disabled.
HEST DMC Structure
Support
HEST DMC (Deferred Machine Check) Structure Support.
Options available: Enabled, Disabled. Default setting is Disabled.
RAS EINJ Mode
BIOS: Send APEI EINJ actions to PSP via CPM EINJ SMI callback;
PSP: Send APEI EINJ actions to RSP via PSP Mailbox.
Option available: BIOS, PSP. Default setting is PSP.