ESMT
F25L004A
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2007
Revision: 1.2 6/32
FUNTIONAL BLOCK DIAGRAM
Address
Buffers
and
Latches
X-Decoder
Flash
Y-Decoder
I/O Butters
and
Data Latches
Serial Interface
Control Logic
CE
SCK
SI
WPSO HOLD
Revision:
1.2 3/32
PIN Description
Symbol Pin Name Functions
SCK Serial Clock
To provide the timing for serial input and
output operations
SI Serial Data Input
To transfer commands, addresses or data
serially into the device.
Data is latched on the rising edge of SCK.
SO Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of
SCK.
CE
Chip Enable
To activate the device when CE is low.
WP
Write Protect
The Write Protect (
WP ) pin is used to
enable/disable BPL bit in the status
register.
HOLD
Hold
To temporality stop serial communication
with SPI flash memory without resetting
the device.
VDD Power Supply To provide power.
VSS Ground
AVR3600 harman/kardon
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