HEIDENHAIN TNC151B - Page 74

Standard (16 LineIAddress Bus
30
rT
CLP
rocessor
CPU
tram IOUcfl
Probe on
SE/ PLC
31.2
EPROM
IC-PI
7
8k x 8
(Char. GM.)
Video
ontrolle
TMS
1937 NL
Gate
Arrays
(Signal
Fast
RAM
2:xX8
Jai tfree
s 9YY:,
r I
Reset
I I-I
I II II II I II I- I I m I
CRU Data Bus
\7 -i/ t/ 77
Standard Data Bus
Block Diagram TNCISI
CLP Processor Board
Drawing-No.:
:-
4820EKO16011 00
Ia
I I I I