Hitachi AP1 - Page 359

------------------------------------------------------------------------HMCS404CL
Table 17 I/O Pin Circuit Type
Without pull-up MOS
With pull-up MOS
Applied
(NMOS
open drain)
CMOS (C)
(A)
(B)
pins
~
input
~;""'
jfi;""'
data
data
data
00 -03,
I/O
V write
Vee
common
'~"~
~HLT
R30 -Rn,
pins
HLT
R40 -R43,
HLT
~outPut
Rso -RS3
output
output
data
data
data
'"
c:
v"~w';~
Vee
'0.
R
60
-R
63
,
'E
Output
~ p",~
<U
pins
HLT
o1~HLT
R
70
-R
73
,
'0
~~HLT
R
so
-R
s3
c:
<U
en
output
output
~~:~ut
data
data
Vee
Input
~
H~
pins
input
HL T input
R
90
-R
93
data
data
Without pull-down MOS
With pull-down MOS (E) Applied pins
(PMOS open drain) (0)
Vee
~~HLT
~HLT
I/O
0-
output
o output
0
4
-0
15
,
data
data
common
R
10
-R
I3
,
pins
Vee
R
10
-R
13
HIT
--
input
Vdisp
HLT
input
data
data
'"
Vee
c:
Vee
'0.
~kO=HLT
Q)
03r<O=HLT
en
output
~
Output
output
data
'0
data
> pins
Vee
R
oo
-R
03
..r::.
.2'
J:
Vdisp
Input
~input
~;"P"' RAO,
data
data
pins
Vee
R
A
1
IV
disp
Vdisp
--
(Note) In the stop mode, H L T signal is "0" and I/O pins are in high impedance state.
(to be continued)
357