The following diagram shows the Program Memory for the I/O Type
MCU
series.
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and in
-
terrupts.
· Location 000H
This vector is reserved for use by the chip reset for program initialization. After a chip reset is ini-
tiated, the program will jump to this location and begin execution.
· Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device receives a
high to low transition, the program will jump to this location and begin execution if the external in-
terrupt is enabled and the stack is not full. For the HT48RU80/HT48CU80, the external interrupt
is known as INT0
.
·
Location 008H
This internal vector is used by the Timer/Event Counter. If a counter overflow occurs, the pro
-
gram will jump to this location and begin execution if the timer interrupt is enabled and the stack
is not full. For the HT48R50A-1/HT48C50-1 and HT48R70A-1/HT48C70-1 devices, which have
dual timers, and the HT48RU80/HT48CU80, which have triple timers, this timer is known as
Timer/Event Counter 0.
·
Location 00CH
This internal vector is used by the Timer/Event Counter. If a counter overflow occurs, the pro
-
gram will jump to this location and begin execution if the timer interrupt is enabled and the stack
is not full. This vector is available for the HT48R50A-1/HT48C50-1, HT48R70A-1/ HT48C70-1
and HT48RU80/HT48CU80 only. The Timer/Event Counter is known as Timer/Event Counter 1.
Note that the HT48R10A-1/HT48C10-1 and HT48R30A-1/HT48C30-1 devices have only one
timer, therefore, this interrupt vector is not used.
Chapter 1 Hardware Structure
21
0 1 4 H
0 0 0 H
0 0 8 H
0 0 C H
0 1 0 H
I n i t i a l i z a t i o n
V e c t o r
E x t e r n a l
I n t e r r u p t V e c t o r
T i m e r / C o u n t e r
I n t e r r u p t V e c t o r
I n i t i a l i z a t i o n
V e c t o r
I n i t i a l i z a t i o n
V e c t o r
E x t e r n a l
I n t e r r u p t V e c t o r
E x t e r n a l
I n t e r r u p t V e c t o r
T i m e r / C o u n t e r
I n t e r r u p t V e c t o r
T i m e r / C o u n t e r 0
I n t e r r u p t V e c t o r
T i m e r / C o u n t e r 1
I n t e r r u p t V e c t o r
H T 4 8 R 1 0 A - 1
H T 4 8 C 1 0 - 1
H T 4 8 R 3 0 A - 1
H T 4 8 C 3 0 - 1
H T 4 8 R 5 0 A - 1
H T 4 8 C 5 0 - 1
0 0 4 H
0 1 8 H
I n i t i a l i z a t i o n
V e c t o r
E x t e r n a l
I n t e r r u p t V e c t o r
T i m e r / C o u n t e r 0
I n t e r r u p t V e c t o r
T i m e r / C o u n t e r 1
I n t e r r u p t V e c t o r
H T 4 8 R 7 0 A - 1
H T 4 8 C 7 0 - 1
1 5 b i t s1 4 b i t s1 4 b i t s
7 F F H
8 0 0 H
F F F H
1 0 0 0 H
1 F F F H
1 6 b i t s
I n i t i a l i z a t i o n
V e c t o r
T i m e r / C o u n t e r 0
I n t e r r u p t V e c t o r
T i m e r / C o u n t e r 1
I n t e r r u p t V e c t o r
U A R T B u s
I n t e r r u p t V e c t o r
H T 4 8 R U 8 0
H T 4 8 C U 8 0
E x t e r n a l I N T 0
I n t e r r u p t V e c t o r
E x t e r n a l I N T 1
I n t e r r u p t V e c t o r
N o t I m p l e m e n t e d
B a n k 1
B a n k 0
1 6 b i t s
T i m e r / C o u n t e r 2
I n t e r r u p t V e c t o r
3 F F H
4 0 0 H
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