Timer Control Registers - TMRC, TMR0C, TMR1C, TMR2C
The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in
three different modes, the options of which are determined by the contents of their respective control
register. For devices with only one timer, the single timer control register is known as TMRC while for
devices with more than one timer, there are two or three timer control registers known as TMR0C,
TMR1C and TMR2C. It is the timer control register together with its corresponding timer registers
that control the full operation of the Timer/Event Counters. Before the timers can be used, it is essen
-
tial that the appropriate timer control register is fully programmed with the right data to ensure its cor
-
rect operation, a process that is normally carried out during program initialization.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width measurement mode, bits 7 and 6 of the Timer Control Register,
which are known as the bit pair TM1/TM0, T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0 respectively,
depending upon which timer is used, must be set to the required logic levels. The timer-on bit,
which is bit 4 of the Timer Control Register and known as TON, T0ON, T1ON or T2ON, depending
upon which timer is used, provides the basic on/off control of the respective timer. Setting the bit
high allows the counter to run, clearing the bit stops the counter. For timers that have prescalers,
bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler. The
prescaler bit settings have no effect if an external clock source is used. If the timer is in the event
count or pulse width measurement mode, the active transition edge level type is selected by the
logic level of bit 3 of the Timer Control Register which is known as TE, T0E, T1E or T2E, depend
-
ing upon which timer is used.
44
I/O Type MCU
N o t i m p l e m e n t e d , r e a d a s " 0 "
b 7
E v e n t C o u n t e r a c t i v e e d g e s e l e c t
1 : c o u n t o n f a l l i n g e d g e
0 : c o u n t o n r i s i n g e d g e
T ET O NT M 0T M 1
T i m e r p r e s c a l e r r a t e s e l e c t
P S C 2
0
0
0
0
1
1
1
1
b 0
P S C 2
P S C 1 P S C 0
P S C 1
0
0
1
1
0
0
1
1
P S C 0
0
1
0
1
0
1
0
1
T i m e r R a t e
1 : 2
1 : 4
1 : 8
1 : 1 6
1 : 3 2
1 : 6 4
1 : 1 2 8
1 : 2 5 6
T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e
1 : e n a b l e
0 : d i s a b l e
O p e r a t i n g m o d e s e l e c t
T M 1
0
0
1
1
T M 0
0
1
0
1
n o m o d e a v a i l a b l e
e v e n t c o u n t e r m o d e
t i m e r m o d e
p u l s e w i d t h m e a s u r e m e n t m o d e
P u l s e W i d t h M e a s u r e m e n t a c t i v e e d g e s e l e c t
1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e
0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e
T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r
T M R C H T 4 8 R 1 0 A - 1 / H T 4 8 C 1 0 - 1
H T 4 8 R 3 0 A - 1 / H T 4 8 C 3 0 - 1
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