Model 1332A
SECTION IV
PRINCIPLES OF OPERATION
Theory
4-1.
INTRODUCTION.
WARNING
4-2. This section contains functional descriptions of
the
1332A keyed to an overall block diagram (figure 8-3).
u
The filament potential is connected to the
-4000 Vdc cathode potential which is
4-3.
CIRCUIT DISCUSSION.
dangerous to life.
4-4. LOW-VOLTAGE POWER SUPPLY (LVPS).
The
LVPS provides regulated +15 V, -15 V and
+lo0 V
operating voltages. It also provides +26 V unregulated
for the high voltage oscillator.
4-5. The +15 V and -15 V supplies function in the
same manner and only the +15 V supply will be dis-
cussed. Line voltage from the secondary of T1 is
rectified by diode bridge
AlCR8 thru AlCRll and
filtered by
AlC14. The +26 V unregulated is applied
to series regulator Q4 through a 1-ampere fuse.
4-6. The output voltage is sensed by
AIR48 and
AIR49 and compared to a reference voltage generated
by
AlU1. AlUl then drives Q1 to maintain the voltage
at AlUl pin 2 equal to the reference voltage at
AlUl
pin 3. AIR47 acts as a current sensor. AIR45 and
AIR46 convert the current to a voltage at pin 10 and
limits the drive to
Q1. AIR44 compensates for tem-
perature drift.
4-7. The
+I00 V supply operates similarly to the
+15 V supply with the following exception. A reference
voltage, developed at
A1U3 pin 4 is applied through a
divider network
(AlR61/AlR62) to the non-inverting
input of
A1U3 (pin 3). Another divider network
AlR59/AlR60 samples the output voltage and applies
it to the inverting input of
A1U3 (pin 2). The output
of
A1U3 (pin 6) drives Q3 to maintain a voltage at
A1U3 pin 2 equal to that applied to A1U3 pin 3.
4-8. AlR58, AlQ14, and AlVR8 form
a
protection
circuit for
AlU3. The circuit protects against large
input-output differential voltages if the output should
become grounded.
AlVR3 and AlVR4 act as crowbar
for the
+110-V output by creating a temporary high
overload during initial turn on.
4-9. HIGH-VOLTAGE POWER SUPPLY (HVPS).
High
voltage oscillator Q4 generates a sine-wave voltage
signal across the primary of
TI. The amplified signal is
rectified by
A3CR1 and filtered by A3C1, A3C2, and
A3R2 to generate the -4000 Vdc cathode voltage.
CRT filament voltage is generated by a sinusoidal
signal from a secondary winding of
T1 and is imposed
on the cathode potential of -4000 Vdc.
4-10. The cathode voltage is sampled by feedback
network
A3C3/A3R4, compared with a reference
current established by high-voltage adjust AlR84, and
fed into regulator
AlU4. The output of A1U4 regulates
the dc level of
T1 base primary winding that drives
high voltage oscillator Q4 and maintains the cathode
voltage at -4000 V.
4-11. Grid voltage is provided by generating a bias
voltage with respect to the cathode voltage. This bias
voltage is generated by a capacitively coupled, clipped
sine-wave signal at the junction of
A3C4 and A3C5.
The upper clipping level is set by Int Limit Adj AlR76.
The lower clipping level is set by the Z-axis dc output.
4-12. Focus voltage is determined by a resistive
divider string including Focus Lim control
A3R13 and
front-panel Focus control
A5R4. Post-accelerator
potential of approximately
+18 kV is supplied by
voltage sextupler assembly A6.
4-13. DEFLECTION AMPLIFIERS.
Since the X- and
Y-
axis amplifiers are identical, only the X-axis ampli-
fier will be discussed.
4-14. The instrument, as shipped from the factory,
is wired for single-ended input operation. Internal
design, however, allows for differential operation
(schematic 2).
4-15. An input signal is applied to A2Q16 which is
a source follower impedance converter. Differential
shunt feedback amplifier,
A2Q17-A2Q20, provides a
signal gain governed by X-GAIN adjust
A2R55.
X
GAIN CTR adjust A2R68 sets the voltage level about
which
A2R55 varies.
4-16. Two balanced feedback amplifiers,
A2Q23/
A2Q24/A2Q27/AZQ28 and A2&25/AZQ26/A2Q29/
A2Q30 comprise the output operational amplifier. A
current input to the output amplifier results in a volt-
age output which drives the horizontal deflection
plates. High-frequency adjustments A2C27 with
A2R75 and A2C28 with A2R76 (lead networks), and
A2R74 with A2C26 (lag network) provide the built-
in rise time of less than 70 nanoseconds.
Scans by ArtekMedia © 2008
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