HP 214B - Page 114

Service
DEL ADV _ DP
DELAY
TP4
EX-OR
A B Y
L L L
H L H
L
H H
H H L
0
S8
DEL =
LO
0
ADV =
HI
DP =
LO
9
ENABLED O NLY
IN D P
t
Model 214B
:0''------ WIDTH
S TART
'.0-'1-'-4 _________ -. .. _ TRIGG ER
Figure 8- 3-3_ Simplified functional diagram of pulse position logic
Delay
With delay selected, the TRIGGER OUT is generated by the negative edge on the signal at 047
collector (TP4). The prevailing conditions in this setting are:
- a high on U3B/
pin 7 thus disabling gate 3B.
- a low
on U3B / pin 9 (due to internal pull-down resistor)
A negative-going edge
at U 1 B/ pin 7 therefore causes U 1 B / pin 10 to go low and U 1 B/ pin 11 to
go high. While the U1B / pin 10 output is routed directly to OR-gate U 20, the U1B/ pin 11
output is delayed via U1 C and U2C, thus generating a 4 ns output pulse at U20 / pin 9. Th is pulse
is inverted by U3C before amplification by trigger amplifier 016 /020_
Double Pulse
With double pulse se lected, the width generation circuit is triggered on both the negative and
positive edge
of the signal at TP4 - thus generating two width cycles per clock period. The
prevailing conditions in this setting are:
- a
low on U3B / pin 7 (due to internal pull-down resistor)
thus enabling gate U3B
- a l
ow on U1B / pin 9 (due to int ernal pull - down re sis tor)
As in the delay settin g, a 4 ns pulse is generated at U20 / pin 9 due to the neg ative edge on the TP4
signa l, this now being routed via gates U3B and U3A to trigger t ~ le width generator. On the positive
edge of the signa l at TP4, a 4 ns output pu l se is generated at U2A / pin 2 (the 4 ns being de termined
by the delay action of gates U 1 A and U2B), this being routed via U3A to trigger the width generator
for the second time within one clock period. A timing diagram illus trating the double pulse logic
sequence
is given in Figure 8- 3- 4.
8- 18
Scans by ArtekMedia => 2009