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HP E1440A - Page 94

HP E1440A
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*CLS
Clear status command.
Syntax
*as
Definition
The *CLS command clears the following:
Error queue
Standard event status register (ESR)
Status byte register bit
5
(STB)
A service request
m
OCAS and OQAS (see IEEE 488.2 specification)
No changes are made to the following:
Status byte register bits
6,
4,
2-0
(STB)
Output queue
Event status enable register (ESE)
Service request enable register (SRE)
After the
*CLS
command the instrument is left in the idle state. The
instrument setting is unaltered
by
the command, though *OPC/*OPC?
actions are canceled.
If
the "CLS command occurs directly after a program message
terminator, the output queue and MAV, bit
4,
in the status byte
register are cleared, and if condition bits
2-0
of the status byte
register are zero, MSS, bit
6
of the status byte register is also zero.
Related Command
SDc
Example
OUTPUT
70911
;
"*CLSt'
5-32
Command
Reference
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

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