Service Manual
After making response to power-up reset, OMAP5912 will output RST_OUT signal, and maintain low
level for some time to reset the peripheral equipment (NOR Flash) of OMAP. For CODEC chip (U501),
its resetting is subject to MPUIO6 of TX OMAP. The reset sequence of OMAP5912 is shown below:
Figure 6-8 Reset Sequence
6.2.4 Clock
OMAP5912 requires two clocks: system clock and 32K clock. The system clock (12MHz, 13MHz or
19.2MHz) can be provided by an external oscillator or square-wave clock signal. This product’s system
clock is provided by
19.2MHz TCXO. Both system clock and 32K clock are provided by ULPD
(Ultralow-power device), which is responsible for OMAP clock management. The clock output by UPLD
is connected to appropriate external interface. See the following figure:
Figure 6-9 External Clock
13
To Next Page
Loading...
