Chapter 2. Architecture and technical overview 25
Draft Document for Review May 28, 2009 1:59 pm 4405ch02 Architecture and technical overview.fm
Figure 2-2 POWER6 processor
The CMOS 11S0 lithography technology in the POWER6 processor uses a 65 nm fabrication
process, which enables:
Performance gains through faster clock rates from 3.5 GHz, 4.2 GHz up to 4.7 GHz.
Physical size of 341 mm.
The POWER6 processor consumes less power and requires less cooling. Thus, you can use
the POWER6 processor in servers where previously you could only use lower frequency
chips due to cooling restrictions.
The 64-bit implementation of the POWER6 design provides the following additional
enhancements:
Compatibility of 64-bit architecture
– Binary compatibility for all POWER and PowerPC® application code level
– Support of partition migration
– Support of virtualized partition memory
– Support of four page sizes : 4 KB, 64 KB, 16 MB, and 16 GB
High frequency optimization
– Designed to operate at maximum speed of 5 GHz
Superscalar core organization
– Simultaneous Multithreading: two threads
In order dispatch of five operations (single thread), seven operations (Simultaneous
Multithreading) to nine execution units:
• Two load or store operations
• Two fixed-point register-register operations
• Two floating-point operations
• One branch operation
POWER5
1.9 GHz
POWER6
core
4.2 GHz
1.9 GHz
POWER6
core
4.2 GHz
Fabric bus
controller
Alti
Vec
Alti
Vec
Ctrl
L3
Memory
Controller
GX Bus
Controller
L2
4 MB
L2
4 MB
Memory+ GX+ Bridge
32 MB
L3 cache
To Next Page
Loading...
Need help?
General