MACHINE INSTRUCTIONS
(Contd)
OP
FOR
OR
(c)
OR
(c)
OR (e)
Pack
NAME
MNEMONIC
o
CODE
MAT
56 RX
OPERANDS
Rl,02(X2,B2)
01(B1I,12
Purge TLB
(p)
Read Direct (p)
Reset Reference
Bit
(c,p)
Set
Clock
(c,p)
Set Clock Comparator
(p)
Set CPU Timer
(p)
Set Prefix (p)
Set
Program Mask (n)
Set
PSW
Key
from
Address
(p)
Set
Storage
Key
(p)
Set
System Mask (p)
Shift
and
Round Decimal (e)
Shift
Left Double (c)
Shift
Left Double Logical
Shift
Left Single (c)
Shift
Left Single Logical
Shift
Right Double (c)
Shift
Right Double Logical
Shift
Right Single (c)
Shift
Right Single Logical
Signal Processor (c.p)
Start
I/O (c,p)
Start
110
Fast
Release
(c.p)
Store
Store Channel
10
(c,p)
Store
Character
Store
CharBCters
under
Mask
StCNfJ
Clock (c)
Store Clock Comparator (pI
Store
Control
(p)
Store CPU Address
(p)
Store CPU
10
(p)
Store
CPU
Timer (p)
Store
Halfword
Store
Multiple
Store Prefix
(p)
Store Then
AND
System
Mask
(p)
Store Then
OR
Symm
Mask
(p)
Subtract
(c)
Subtract
(c)
Subtract
Decimal (c)
Subtract
Hallword (c)
Subtract
Logical (c)
Subtract
Logical (c)
Supervisor Call
Test
and
Set
(c)
Test
Channel (c,p)
Test
I/O (c,p)
Test
under
Mask (c)
Translate
Translate
and
Test (e)
Unpack
Write Direct (p)
Zero
and
Add Decimal (cl
F1oatinltPoint Instructions
NAME
Add
Normalized. Extended (c,x)
Add Normalized. Long (c)
Add Normalized, Long (c)
Add
Normalized,
Short
(c)
Add
Normalized,
Short
(c)
Add Unnormalized, Long (c)
Add Unnormalized. Long (c)
Add
Un
normalized.
Short
(c)
Add Unnormalized.
Short
(c)
c. Condition
code
is
set.
n. New condition
code
is
loaded.
Page
2·2
01
DC
PACK
PTLB
ROD
RRB
SCK
SCKC
SPT
SPX
SPM
SPKA
SSK
SSM
SRP
SLOA
SLOL
SLA
SLL
SROA
SROL
SRA
SRL
SIGP
SID
SIOF
ST
STiOC
STC
STCM
STCK
STCKC
STCTL
STAP
STIOP
STPT
STH
~TM
STPX.
STNSM
STOSM
SR
S
SP
SH
SLR
SL
SVC
TS
TCH
TID
TM
TR
TRT
UNPK
WRO
ZAP
96
SI
06
SS
F2
SS
B200
S
85
SI
B213 S
B204 S
B206 S
B208
S
B210 S
04
RR
B20A
S
08
RR
80 S
FO
SS
8F
RS
80
RS
8B
RS
89
RS
BE
RS
8C
RS
8A
RS
sa
RS
AE
RS
9COO
S
9COI S
50
RX
B203
S
42
RX
BE
RS
B205 S
B207 S
B6 RS
B212 S
B202 S
B209 S
40
RX
00
RS
B211 S
AC
SI
AD
SI
lB
RR
5B
RX
FB
SS
4B
RX
IF
RR
5F
RX
OA
RR
93
S
9FOO
S
9000
S
91
SI
DC SS
00
SS
F3
SS
84
SI
F8
SS
01
(L,Bl
).02(B2)
01
(L
I,Bl
),02(L2,B2)
01(Bl).12
02(B2)
02(B2)
02(B2)
02(B2)
02(B21
Rl
02(B21
R1,R2
02(B2)
01(L1,Bll,02(B2),13
Rl,02(B2)
Rl,02(B2)
Rl,02(B2)
Rl.02(B2)
Rl,02(B2)
Rl,02(B2)
Rl,02(B2)
Rl,02(B2)
Rl,R3,02(B2)
02(B2)
02(B2)
Rl,02(X2,B2)
02(B2)
R
1,02(X2,B2)
Rl,M3.02(B2)
02(B2)
02(B2)
Rl,R3,02(B2)
02(B2)
02(B2)
02(B2)
Rl.02(X2.B2)
Rl,R3,D2(B2)
02(B2)
01(B1I,12
D1(B1I,12
Rl,R2
Rl,02(X2.B2)
01(
L1,B1I
,02(
L2,B2)
Rl,02(X2.B2)
Rl,R2
Rl.D2(X2,B2)
I
02(B2)
02(B2)
02(B21
01(B1I,I2
01
(L,Bl ).D2(B2)
01
(L,Bl
).02(B2)
D1(L1,Bl ).D2(L2,B2)
01(B1),I2
01(L1,B1I,D2(L2,B2)
OP
FOR-
MNEMONIC
AXR
AOR
AD
AER
AE
AWR
AW
AUR
AU
CODE
MAT
36
RR
2A RR
6A
RX
3A
RR
7A RX
2E RR
6E RX
3E RR
7E RX
OPERANDS
Rl.R2
Rl,R2
Rl.02(X2.B2)
Rl,R2
Rl,02(X2,B2)
Rl.R2
Rl.02(X2,B2)
Rl,R2
Rl,02(X2,B2)
p. Privileged instruction.
x.
Extended
precision floating·point.