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Icom IC-701

Icom IC-701
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6-3
PLL
(Phase
Locked
Loop)
UNIT
6-3-1
LOCAL
OSCILLATOR
CIRCUIT
Q1-Q6
are
local
oscillator
circuits
for
the
conversion
type
PLL.
Each
circuit,
Q1-O6
is
functional
for
each
band
respectively;
for
example,
Q1
is
for
the
1.8MHz
band
and
Q6
is
for
the
28MHz
band.
Each
oscillator
circuit
is
basically
the
same,
being
a
doubler
with
3rd
overtone
crystals.
XTAL
OUTPUT
28
MHz
40.625MHz
81.25MHz
For
example,
X1
of
the
1.8MHz
oscillator
is
a
3rd
overtone
crystal
(27.125MHz)
and
has
L2
in
series,
which
is
for
the
X1
oscillating
frequency
adjustment.
The
output
tuning
circuit
Connected
to
the
Q1
collector
is
tuned
for
54.25
MHz,
which
is
double
the
frequency
of
the
fundamental
crystal
oscillator
frequency.
The
operation
of
Q2-Q6
is
exactly
the
same
as
that
of
01,
except
the
output
fre-
quencies
are
different.
6-3-2
VXO
(Variable
Frequency
Crystal
Oscillator)
CIRCUIT
This
circuit
is
for
the
oscillation,
by
100Hz
steps,
of
the
lowest
two
digits
(0.0
-
9.9KHz)
of
the
VCO
output
fre-
quency
of
the
PLL
circuit.
The
VXO
circuit
consists
of
LS!
BLOCK
DIAGRAM
Output
Data
Selector
Q7,
Q8,
D9,
X7,
18,
etc.
QO8
oscillates
on
the
15MHz
range
using
X7,
D9,
D10,
and
L18,
and
the
oscillating
frequency
is
altered
in
100Hz
steps
by
the
voltage
supplied
from
the
D/A
(Digital
to
Analog)
converter.
Q7
triples
the
output
signal
from
O8
and
supplies
about
45MHz
signal
to
the
mixer
circuit
of
IC7.
6-3-3
MIXER
AND
AMPLIFIER
CIRCUIT
The
local
oscillator
output
and
VCO
output
are
mixed
by
IC6
and
the
mixed
signal
is
taken
from
Pins
3
and
13
of
IC6.
The
output
signal
is
filtered
by
L13
and
L14,
tuned
for
42-44Hz,
to
supply
the
signal
to
IC7.
The
output
signal
of
the
VXO
circuit
is
also
supplied
to
IC7
to
be
mixed
with
the
signal
from
IC6.
The
difference
of
these
two
signals
(IMHz
-
3MHz)
is
filtered
by
a
low-pass
filter
and
is
amplified
by
IC8
up
to
the
level
of
more
than
1.6Vp-p.
6-3-4
PLL
LSI
CIRCUIT
The
output
from
IC8
is
the
input
to
the
LSI,
Pin
2.
The
LS!
contains
PLL
and
control
circuits.
To
drive
the
reference
frequency
of
the
PLL,
a
SMHz
crystal
oscillator
is
connected
to
Pins
3
and
4.
This
frequency
is
divided
into
1/500
by
the
fixed
frequency
divider
in
the
LSI
and
becomes
the
accurate
frequency
of
10KHz.
The
input
from
Pin
2
is
divided
by
the
Programmable
divider
in
the
LSI
from
1/100-1/299
which
is
decided
by
the
controller,
fed
into
the
phase
frequency
detector
with
the
reference
frequency
of
10KHz.
The
output
is
taken
from
Pin
40
in
the
form
of
a
pulse
from
the
phase
detector
according
to
these
two
input’s
difference
of
phase.
The
controller
circuit
consists
of
two
sets
of
a
4-1/2
digit
BCD
up-down
B,
A,
DC
BA,
D,
C,
By
A,D,C,
B,
A,
D,
CyB)
Ag
to
Frequency
Display
Ay
i,
Dy
Cy
By
Ag
D,
C)B,
A,
UNE
TT
F}}})]})
UP/DOWN
Control
UD
ByA,D;
Ay
CK
UP/DOWN
Counter
A
XYZ
CL
fy
FF
Fi
Fo
Koki
KoKy
Ky
EE
ei
DIGIT
Counter
GANG
Control
GANG
G
Control
COUNTER
SWITCH
COUNTER
SL
Switch
Frequency
control
Pulse
input
CLOCK
XYZ
CL
STEP
Switch
B,
A,
D;
Ay
XYZ.
al
Divider
HI
FLKK
KK,
Programmable
Divider
UP/DOWN
Counter
B
Fy
3
Fo
F,
Fy
Kok;
Ko
KyKy
Phase
Detector
Divide
ratio
DIGIT
Counter
D
IN
Oscillator
q
Crystal
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Tee
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Sat
TTT
One TON
ORE
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SENN
SEO
SEN
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