Icom IC-701

6-4-3 MEMORY CONTROL CIRCUIT
Pin 5 of I1C5 is connected to the VFO switch on the front
panel and changes from H to L or L to H if the switch is
changed. The delay circuits R17 and C5 are connected to
Pin 6 so pulses of positive edge and negative edge are taken
out and fed to Pin 13 of IC4. The monostable multivibrator
is made up of IC4, a NOR gate circuit, and an inverter.
The Low level pulse output is taken from Pin 11 and the
High level pulse from Pin 4. IC6 and IC7 are the 3 bit band
memory circuits. The chart shows the band codes assigned
to each.
1C7 Pin13 IC6 Pin 1 IC6 Pin13
The exclusive OR gates made up of three units of IC5
compares the contents of this memory with the band codes
consisting of D5-D11. If they are the same, Pin 12 of IC8
goes LOW, and if they are different, it goes HIGH. A
one-shot pulse from Pin 4 of [C4 is fed to Pin 13 of IC8
and as it is a NAND gate IC, its output is taken from Pin 11
only when the memories are different. If a one-shot pulse
is generated, the pulse is added to Pin 11 and Pin 3 of the
CK terminals of IC6 and IC7 when its pulse is terminated
and the output of the band code is added to the D input,
and this band is memorized.
The output of IC8, Pin 11, is connected with Pin 9. The
Power On Clear (POC) pulse, which becomes a 100ms
HIGH level pulse when the power source switch is turned
ON, and the SDP pulse which occurs when the band is
changed, are input to Pin 8. So it follows that Pin 10 of
IC8 is supplied with a HIGH level pulse in both cases.
6-4-4 BAND EDGE DETECTION CIRCUIT
The output of IC8 Pin 10 is combined with IC7 Pin 6. This
works as a monostable multivibrator since this is added to
Pin 4 of RESET from the O output through the delay
circuit. Pin 1 of IC7 is fed to IC8 Pin 5 and to [C10 Pin 8
of the RESET through the differentiation circuitry. Pin 1
of 2 gates of IC8 works as a multivibrator and gives off
about seven pulses for one shot pulse from Pin 1 of IC7.
iIC10 works as a 2 bit shift register and at first Pin 13 goes
HIGH, and Pin 1 goes LOW by the one-shot pulse from IC7.
Then the output of IC8 is added to Pin 3 and Pin 11 of the
CK terminals through the inverter 1C4 and under the
circumstances preset by the input of IC7, Pin 13 is HIGH,
and Pin 1 is LOW. The output of Pin 13 is fed to Pin 1 of
1C12 and since this is an OR gate, it’s output, fed to 1C1 in
the PLL unit becomes the FCL signal. If the first pulse
from the output of the inverter, [C4, goes to 1C10, Pin 13
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