IEC 30 Series - Page 25

SECTION 3
• Outputs from the logic section are:
Start/Stop command line (R283, C1l5
junction).
Sweep run command line, S6 - 2B wiper.
Last cycle completion circuit defeat,
S6 - lA pole.
3-8. SWEEP GENERATOR (F34)
The Sweep Generator consists of operational
integrator Q51, ICI5; voltage-level comparator
ICI6, Q62; and input-voltage reversing switch
Q65. Sweep time vernier control R287 applies
a variable voltage level to an integrator input
resistor. Sweep time range switch S7 selected
an appropriate feedback capacitor for the oper-
ational integrator. As the voltage at IC15 pin
12 rises, a level is reached which will cause
comparator IC 16 to reverse. This action ener-
gizes Q65 and causes voltage of an opposite
polarity to appear across a portion of the
integrator input resistor, reversing the integra-
tor. This results in a larger charging current
and faster retrace in the sweep. As this action
occurs, a new reference level is set into com-
parator IC 16 pin 4. When the integrator level
has reduced sufficiently, the comparator will
again reverse, establishing original conditions.
Q66 and Q64 are activated by a logic signal which
stalls integrator action by shorting the timing
capacitors. Q63 is a buffer amplifier which
supplies a "sweep running" signal to the Logic
Section.
3-9. OUTPUT LIMIT CIRCUIT
The Output Limit circuit is a d-c analog
computer which turns on the OUTPUT Limit
light if the amplifier is being driven close to
saturation. IC 18 is an operational amplifier
which sums a d-c analog of the signal amplitude
with a portion of the d-c offset signal. The
summation is fed to a level detector (Q48,
Q49) which
turns on DS2 light if the level is
too high.
Since the offset signal is bipolar, diodes CR48
and C49 are required to steer the currents in
order to sum the absolute value of the offset.
3-5