IEC 30 Series - Logic Sequence Timing Diagram

3-6
SECTION 3
•
T =0
EXTSIGTO~
TR IG I SYNC BNC I
TP24~
I
IC14-PIN3 ~
IC14-PINS 4 ~ r---
& 12 GATE MODE l------J
I
IC14-PINS 4 & 12 If-----
TRIGGER MODES I SYSTEM OPERATE LEVEL
04 (REMAINS ON UNTIL RESET BY
TP25 L - ~;S~E~ ~;O~ FUNCT ION SHOWN BELOW)
CR67 ANODE MAIN I
LOOP SO WAVE } ALL GATE & TRIGGER
TP25 :ESET MODES EXCEPT SWEEP
I
r----- TR I GG ER
ICI4-PIN II TP25 RE~ET }.J GOES NEG WHEN BOTH IC14 PINS 4 & 12
TP29 ' L A~ID CR67 ANODE ARE POS)
SWEEP RETRACE nL.....- ~ SWP TR I GGER MODE ONLY
START STOP CKT TIMING DIAGRAM
TP25
CR53 ANODE
CR56 ANODE MAIN
LOOP SO WAVE I .- ALLOWS MAIN LOOP OPEN IF EITHER
TP30 CR53 ANODE OR CR56 ANODE ARE HIGH J......-----""'----
TP19.1 I ~ CLAMPED AT THI S LEVEL
I BY 054 & 055
Figure 3-2. Logic Sequence Timing Diagram (F32. F33. F34)