PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 Architecture
This document provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual. The reference manual is not recommended for those new to the PSoC™ 6 MCU, nor as a guide for developing PSoC™ 6 MCU applications. Instead, users should consult the PSoC™ 61 datasheet, PSoC™ 62 datasheet, Peripheral Driver Library (PDL) documentation, Application Notes, and Code Examples.
Function Description
The PSoC™ 6 MCU is a high-performance, ultra-low-power, and secure MCU platform, purpose-built for IoT applications. The CY8C6xx5 product family (CY8C61x5 and CY8C62x5), based on the PSoC™ 6 MCU platform, combines a dual-core microcontroller with built-in programmable peripherals. It integrates low-power flash technology, high-performance analog-to-digital conversion, low-power comparators, touch sensing, a serial memory interface with encryption, a secure digital host controller (SDHC), and standard communication and timing peripherals.
The device features a 32-bit dual CPU subsystem with a 150-MHz Arm® Cortex®-M4F (CM4) CPU and a 100-MHz Cortex®-M0+ (CM0+) CPU. Both CPUs include a single-cycle multiply, floating point unit (FPU) on the CM4, and Memory Protection Units (MPU). User-selectable core logic operation is available at either 1.1 V or 0.9 V. The memory subsystem includes 512-KB application flash, 32-KB auxiliary flash (AUXFlash), and 32-KB supervisory flash (SFlash) with read-while-write (RWW) support, and two 8-KB flash caches (one for each CPU). It also features 256-KB SRAM with programmable power control and retention granularity, and a one-time-programmable (OTP) 1-Kb eFuse array.
The PSoC™ 6 MCU supports six power modes for fine-grained power management, including Deep Sleep mode with SRAM retention, and an on-chip DC-DC Buck converter. A backup domain and real-time clock are also included. Flexible clocking options are provided with on-chip crystal oscillators, a Phase-Locked Loop (PLL) for multiplying clock frequency, an Internal Main Oscillator (IMO), an ultra-low-power Internal Low-Speed Oscillator (ILO), and a Frequency Locked Loop (FLL) for multiplying IMO frequency.
The Quad-SPI (QSPI)/Serial Memory Interface (SMIF) supports Execute-In-Place (XIP) from external Quad SPI flash with on-the-fly encryption and decryption, and a 4-KB cache for enhanced XIP performance and lower power. It supports single, dual, quad, dual-quad, and octal interfaces. The Segment LCD drive supports up to 63 segments and 8 commons, operating in System Deep Sleep mode.
Serial communication is handled by seven run-time configurable Serial Communication Blocks (SCBs), six of which are configurable as SPI, I²C, or UARTs, and one Deep Sleep SCB configurable as SPI or I²C. A USB full-speed device interface is also available. The device includes one CAN FD block for Controller Area Network with Flexible Data-Rate communication.
Timing and Pulse-Width Modulation (PWM) are managed by twelve Timer/Counter Pulse-Width Modulators (TCPWMs) supporting center-aligned, edge, and pseudo-random modes, and comparator-based triggering of Kill signals. Programmable analog features include a 12-bit 2-Msps SAR ADC with differential and single-ended modes and a 16-channel sequencer with result averaging, two low-power comparators available in Deep Sleep and Hibernate modes, and a built-in temperature sensor connected to the ADC. Up to 64 programmable GPIOs are available, with two smart I/O ports enabling boolean operations on GPIO pins during system Deep Sleep, programmable drive modes, strengths, and slew rates, and two overvoltage-tolerant (OVT) pins.
Capacitive sensing is supported by Capacitive Sigma-Delta (CSD) for best-in-class SNR, liquid tolerance, and proximity sensing, enabling dynamic usage of both self and mutual sensing, and automatic hardware tuning (SmartSense™). Authentication during boot is provided using hardware hashing. Cryptography accelerators offer hardware acceleration for symmetric and asymmetric cryptographic methods and hash functions, along with a True Random Number Generator (TRNG) function. An eight-counter profiler provides event or duration monitoring of on-chip resources.
Important Technical Specifications
- CPU Subsystem:
- 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, FPU, and MPU.
- 100-MHz Cortex®-M0+ (CM0+) CPU with single-cycle multiply and MPU.
- User-selectable core logic operation: 1.1 V or 0.9 V.
- Both CPUs have 8-KB instruction caches with four-way set associativity.
- Cortex®-M4 supports Arm®v7-M Thumb instruction set; Cortex®-M0+ supports Armv6-M Thumb instruction set.
- Nested Vectored Interrupt Controllers (NVIC) for rapid and deterministic interrupt response.
- Extensive debug support: SWJ, ETM (CM4), 4-KB Micro Trace Buffer (MTB) (CM0+), breakpoints, watchpoints.
- Inter-processor communication (IPC) hardware.
- Memory Subsystem:
- 512-KB application flash, 32-KB auxiliary flash (AUXFlash), 32-KB supervisory flash (SFlash) with RWW support.
- 256-KB SRAM with programmable power control and retention granularity.
- One-time-programmable (OTP) 1-Kb eFuse array.
- Power Modes:
- Six power modes for fine-grained power management.
- Deep Sleep mode with SRAM retention.
- On-chip DC-DC Buck converter.
- Backup domain and real-time clock.
- Clocking Options:
- On-chip crystal oscillators (ECO, WCO).
- Phase-locked loop (PLL) (10.625–150 MHz output range).
- Internal main oscillator (IMO) (8 MHz).
- Ultra-low-power internal low-speed oscillator (ILO) (32.768 kHz nominal).
- Frequency locked loop (FLL) (24–100 MHz output range).
- Quad-SPI (QSPI)/Serial Memory Interface (SMIF):
- Execute-In-Place (XIP) from external Quad SPI flash.
- On-the-fly encryption and decryption.
- 4-KB cache.
- Serial Communication Blocks (SCBs):
- Seven configurable SCBs (SPI, I²C, UART).
- USB full-speed device interface.
- CAN FD:
- One CAN FD block.
- Flexible data-rate (FD) up to 64 data bytes per message, max 8 Mbps.
- Time-Triggered (TT) communication on CAN (ISO 11898-4: 2004).
- Timer, Counter, and PWM (TCPWM):
- Twelve TCPWMs.
- 16- or 32-bit counter widths.
- Analog:
- 12-bit 2-Msps SAR ADC with 16-channel sequencer.
- Two low-power comparators.
- Built-in temperature sensor.
- GPIOs:
- Up to 64 programmable GPIOs.
- Two smart I/O ports (16 I/Os) with boolean operations.
- Programmable drive modes, strengths, and slew rates.
- Two overvoltage-tolerant (OVT) pins.
- Capacitive Sensing:
- Capacitive Sigma-Delta (CSD) for SNR, liquid tolerance, proximity sensing.
- Automatic hardware tuning (SmartSense™).
- Cryptography Accelerators:
- Hardware acceleration for symmetric (AES, DES, TDES) and asymmetric (RSA, ECC) cryptographic methods, hash functions (SHA1, SHA2, SHA3), CRC, PRNG, and TRNG.
- Profiler:
- Eight counters for event or duration monitoring.
Usage Features
- Dual-Core Operation: The PSoC™ 62 series allows both CM4 and CM0+ CPUs for applications, while the PSoC™ 61 series reserves CM0+ for system functions, with CM0+ entering CPU Deep Sleep mode when not executing system functions.
- Inter-Processor Communication (IPC): Provides communication and synchronization between multiple processors using IPC channels and interrupts. Supports mutual exclusion locks and message passing.
- Fault Monitoring: Centralized fault report structures monitor access violation faults at protection units (MPU, SMPU, PPU) and flash controller bus errors. Supports logging fault data, soft reset on fault detection, interrupt on fault detection, trigger output to DMA, and external fault handling via pin output.
- Interrupts and Exceptions: Supports up to 174 system interrupts with Nested Vectored Interrupt Controllers (NVIC) for rapid and deterministic response. Configurable priority levels and support for level-triggered and pulse-triggered signals. Wakeup Interrupt Controller (WIC) enables interrupt detection in Deep Sleep mode.
- Protection Units: MPU, SMPU, and PPU enforce security by restricting bus transfers based on protection attributes and memory regions.
- DMA and DMAC Controllers: Facilitate independent data transfers between memory, peripherals, and registers. Supports single, 1D, 2D, memory-copy, or scatter-transfer modes with configurable source/destination address increments and interrupt/trigger generation.
- Nonvolatile Memory Programming: SROM API library for flash management (Program Row, Erase Flash, Blow eFuse) and system management (checksum). System calls can be performed by CM0+, CM4, or DAP.
- Boot Code: Validates and starts product firmware, applies trims and configurations, and authenticates applications based on life-cycle stages and protection states.
- Device Security: Nonvolatile and irreversible life cycle stages limit program and debug access. Shared memory protection unit (SMPU) provides programmable flash, SRAM, and register protection. Hardware-based encryption and decryption.
- Power Supply and Monitoring: Multiple on-chip regulators, Power-On Reset (POR), Brownout Detect (BOD), Overvoltage Protection (OVP), and Low-Voltage Detect (LVD) circuits ensure stable operation and failure protection.
- Device Power Modes: Four system power modes (LP, ULP, Deep Sleep, Hibernate) and three CPU power modes (Active, Sleep, Deep Sleep) for optimized power consumption.
- Clocking System: Flexible clock sources (IMO, ECO, ILO, WCO, EXTCLK) and clock generation (FLL, PLL) with configurable dividers for peripheral clocks.
- Reset System: Multiple reset sources (POR, BOD, XRES, WDT, software-initiated, logic-protection fault, clock-supervision logic, Hibernate wakeup) with detection mechanisms.
- I/O System: Programmable GPIOs with analog and digital capabilities, various drive strength modes, slew rate control, edge-triggered interrupts, and Smart I/O for boolean functions.
- Serial Communications Block (SCB): Supports SPI, UART, and I²C protocols with FIFO, EZ, and CMD_RESP buffer modes.
- Serial Memory Interface (SMIF): Master interface to external serial memory devices, supporting single-SPI, dual-SPI, quad-SPI, or octal-SPI communication. XIP mode maps external memory to internal address space.
- CAN FD Controller: Complies with ISO 11898-1 and ISO 11898-4 (TTCAN). Supports flexible data-rate, acceptance filtering, and dedicated RX/TX buffers.
- Timer, Counter, and PWM (TCPWM): Configurable as timer, counter, PWM, or quadrature decoder. Supports various counting modes, clock prescaling, and interrupt/trigger generation.
- Universal Serial Bus (USB) Host/Device Mode: USB 2.0 compliant, supporting full-speed operation, various transfer types (Bulk, Control, Interrupt, Isochronous), and logical transfer modes (No DMA, Manual DMA, Automatic DMA).
- LCD Direct Drive: Supports STN and TN segment LCDs with up to 63 segments and 8 commons. Various drive methods (Digital correlation, PWM at 1/2, 1/3, 1/4 bias) and digital contrast control.
Maintenance Features
- Firmware Updates: Flash memory can be programmed by CM0+/CM4 CPU or DAP, allowing for in-field firmware upgrades.
- Debug Interfaces: JTAG or SWD interfaces provide programming and debugging capabilities. SWV (CM4) and MTB (CM0+) offer real-time trace information.
- Fault Analysis: Fault report structures capture detailed information on protection violations and bus errors, aiding in failure analysis and recovery.
- Watchdog Timers: Free-running WDT and Multi-Counter WDTs (MCWDT) automatically reset the device in case of unexpected firmware execution, preventing system crashes.
- Clock Calibration: Hardware calibration counters compare clock sources to trim lower accuracy oscillators (e.g., ILO against ECO).
- Reset Cause Detection: Registers (RES_CAUSE, RES_CAUSE2) record occurrences of WDT, software, logic-protection fault, and clock-supervision resets for post-reset analysis.
- Memory Buffer Management: SRAM controllers include write buffers to optimize performance and ensure memory consistency.
- Power Management: Fine-grained power management modes (LP, ULP, Deep Sleep, Hibernate) allow applications to minimize average power consumption by selectively enabling/disabling clocks and peripherals.
- Register Access: Comprehensive register lists are provided for detailed configuration and status monitoring of all device components.
- SROM API Library: Provides standardized system calls for flash and eFuse management, ensuring controlled and secure operations.
- Device Security Features: Life-cycle stages and protection states are governed by eFuse, providing irreversible security settings. Protection units (MPU, SMPU, PPU) restrict unauthorized access to memory and peripherals.
- Hardware-Based Encryption: Cryptographic block accelerates symmetric and asymmetric encryption/decryption, hashing, and random number generation, enhancing data security.
To Next Page
Need help?
General
