Reference manual 596 002-27293 Rev. *E
2023-09-06
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture
Universal Serial Bus (USB) device mode
32.4.3 Automatic DMA mode
This is the Automatic memory management mode with auto DMA access. The CPU programs the initial buffer size
requirement for IN/OUT packets and informs the arbiter block of the endpoint configuration details for the
particular application. The block then controls memory partitioning and handling of all memory pointers. During
memory allocation, each active IN endpoint (set by the USBDEV_EP_ACTIVE and USBDEV_EP_TYPE registers) is
allocated a small amount of memory configured using the USBDEV_BUF_SIZE register (32 bytes for each of the
eight endpoints). The remaining memory (256 bytes) is left as common area and is common for all endpoints.
In this mode, the memory requirement is less and it is suitable for full-speed isochronous transfers up to 1023
bytes.
When an IN command is sent by the host, the device responds with the data present in the dedicated memory
area for that endpoint. It simultaneously issues a DMA request for more data for that EP. This data fills up the
common area. The device does not wait for the entire packet of data to be available. It waits only for the
(USBDEV_DMA_THRES_MSB, USBDEV_DMA_THRES) number of data available in the SRAM memory and begins
the transfer from the common area.
Similarly, when an OUT command is received, the data for the OUT endpoint is written to the common area. When
some data (greater than USBDEV_DMA_THRES_MSB, USBDEV_DMA_THRES) is available in the common area, the
arbiter block initiates a DMA request and the data is immediately written to the device. The device does not wait
for the common area to be filled.
This mode requires configuration of the USBDEV_DMA_THRES and USBDEV_DMA_THRES_MSB registers to hold
the number of bytes that can be transferred in one DMA transfer (32 bytes). Similarly, the burst count of the DMA
should always be equal to the value set in the USBDEV_DMA_THRES registers. Apart from the DMA configuration,
this mode also needs the configuration of the USBDEV_BUF_SIZE for the IN and the OUT buffers and the
USBDEV_EP_ACTIVE and the USBDEV_EP_TYPE registers.
Each DMA channel has two descriptors and both of them are used in this mode. Each descriptor is considered as
a data chunk of 32 bytes and it executes according to the trigger mechanism. The descriptors are chained and
hence 64 bytes can be transferred without firmware interaction. When both descriptors complete the endpoint
DMA done interrupt and the DMA error interrupt triggers (due to the lack of data to transfer). The descriptors are
updated to advance the source SRAM (IN endpoint) or destination SRAM (OUT endpoint) pointer locations and
then enabled again. This sequence continues till all data is transferred.
The steps for IN and OUT transactions using automatic DMA mode are shown in Figure 32-7
and Figure 32-8.
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