Reference manual 261 002-27293 Rev. *E
2023-09-06
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture
Device power modes
some content. Note that these registers are reset by other reset events. On a Hibernate wakeup event, the
HIBERNATE bit [31] of the PWR_HIBERNATE register is cleared.
The brownout detect (BOD) block is not available in Hibernate mode. As a result, the device does not recover from
a brownout event in Hibernate mode. Do not enter Hibernate mode in applications that require brownout
detection, that is, applications where the supply is not stable. In addition, make sure the supply is stable for at
least 250 µs before the device enters Hibernate mode. To prevent accidental entry into Hibernate mode in
applications that cannot meet these requirements, an option to disable the Hibernate mode is provided. Set the
HIBERNATE_DISABLE bit [30] of the PWR_HIBERNATE register to disable Hibernate mode in the device. Note that
this bit is a write-once bit during execution and is cleared only on reset. Debug functionality will be lost and the
debugger will disconnect on entering Hibernate mode.
19.2.5 Other operation modes
In addition to the power modes discussed in the previous sections, there are three other states the device can be
in – Reset, Off, and Backup states. These states are determined by the external power supply and XRES
connections. No firmware action is required to enter these modes nor an interrupt or wakeup event to exit them.
19.2.5.1 Backup domain
PSoC™ 6 offers an independent backup supply option that can be supplied through a separate Vbackup pin. For
details on the backup domain and the powering options, see the “Backup system”
on page 270. This domain
powers a real-time clock (RTC) block, WCO, and a small set of backup registers. Because the power supply to
these blocks come from a dedicated Vbackup pin, these blocks continue to operate in all CPU and system power
modes, and even when the device power is disconnected or held in reset as long as a Vbackup supply is provided.
The RTC present in the backup domain provides an option to wake up the device from any CPU or system power
mode. The RTC can be clocked by an external crystal (WCO) or the internal low-speed oscillator (ILO). However,
the ILO is available only if the device is powered – the device should not be in the off or reset state. Using ILO is
not recommended for timekeeping purpose; however, it can be used for wakeup from Hibernate power mode.
19.2.5.2 Reset state
Reset is the device state when an external reset (XRES pin pulled low) is applied or when POR/BOD is asserted.
Reset is not a power mode. During the reset state, all the components in the device are powered down and I/Os
are tristated, keeping the power consumption to a minimum.
19.2.5.3 Off state
The off state simply represents the device state with no power applied. Even in the device off state, the backup
domain can continue to receive power (Vbackup pin) and run the peripherals present in that domain. The reset
and off states are discussed for completeness of all possible modes and states the device can be in. These states
can be used in a system to further optimize power consumption. For instance, the system can control the supply
of the PSoC™ 6 MCU by enabling or disabling the regulator output powering the device using the PMIC interface.
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