Reference manual 331 002-27293 Rev. *E
2023-09-06
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture
Watchdog timer
24.3.3 Watchdog interrupt
In addition to generating a device reset, the WDT can be used to generate interrupts. Note that interrupt servicing
and watchdog reset cannot be used simultaneously using the free-running WDT.
The watchdog counter can send interrupt requests to the CPU in CPU Active power modes and to the wakeup
interrupt controller (WIC) in CPU Sleep and Deep Sleep power modes. In addition, the watchdog is capable of
waking up the device from Hibernate power mode. It works as follows:
• CPU Active mode: In Active power mode, the WDT can send the interrupt to the CPU. The CPU acknowledges
the interrupt request and executes the ISR. Clear the interrupt in the ISR.
• CPU Sleep or Deep Sleep mode: In this mode, the CPU is powered down. Therefore, the interrupt request
from the WDT is directly sent to the WIC, which then wakes up the CPU. The CPU acknowledges the interrupt
request and executes the ISR. Clear the interrupt in the ISR.
• Hibernate mode: In this mode, the entire device except a few peripherals (such as WDT and LPCOMP) are
powered down. Any interrupt to wake up the device in this mode results in a device reset. Hence, there is no
interrupt service routine or mechanism associated with this mode.
For more details on device power modes, see the “Device power modes”
on page 256.
Because of its free-running nature, the WDT should not be used for periodic interrupt generation. Use the MCWDT
instead; see
“Multi-counter WDTs” on page 332. The MCWDT counters can be used to generate periodic
interrupts. If absolutely required, follow these steps to use the WDT as a periodic interrupt generator:
1. Unlock the WDT if this is the first update to the WDT registers after a deep sleep or hibernate wakeup, or a
device reset.
2. Write the desired IGNORE_BITS in the WDT_MATCH register to set the counter resolution to be used for the
match.
3. Write the desired match value to the WDT_MATCH register.
4. Set the WDT_MATCH bit in the SRSS_INTR register to clear any pending WDT interrupt.
5. Enable the WDT interrupt to CPU by setting the WDT_MATCH bit in SRSS_INTR_MASK.
6. Enable SRSS interrupt to the CPU by configuring the appropriate ISER register (See the
“Interrupts” on
page 61 for details).
7. In the ISR, unlock the WDT; clear the WDT interrupt and add the desired match value to the existing match
value. By doing so, another interrupt is generated when the counter reaches the new match value (period).
To Next Page
Loading...