Intel 80386

MEMORY INTERFACING
tRD: Data delay from Read (MRDC#)
(4 x CLK2 period) -
PAL RegOut Max - xcvr. prop Min
-
80386 Data Setup Min
(4 x 31.25) -
12 - 6
-
10
= 97 nanoseconds
tDF: read (MRDC# rise) to Data Float
(4 x CLK2 period) -
PAL RegOut Max· + PAL RegOut Min
+ xcvr. Enable Min
(4x31.25) - 12 + 0
+ 3
= 116 nanoseconds
To pipeline the address outputs for sequential EPROM accesses, the address decoder logic
must generate the Next Address (NA#) signal. Note that the initial
EPROM cycle follow-
ing the idle cycle cannot be address pipelined because there
is no previous bus cycle. In
addition, the bus cycle following the last
EPROM access is pipelined regardless of which
device it accesses, because the address
is output before the bus cycle destination can be
determined.
6.2.7 SRAM Interface
In the SRAM interface, the OE# input of each SRAM device is connected to the MRDC#
signal from the bus controller; the WE# input of each
SRAM device is driven by the MWTC#
signal. Because
it is possible to write to only some bytes of a doubleword, the MWTC#
signal cannot connect directly to the WE# inputs. Each WE# input must
be qualified by the
latched
80386 byte-enable signals (BE3#-BEO#).
Figure 6-7
shows the signal timing for bus cycles to an Intel SRAM, which has a
100-nanosecond access time. The timing
is essentially the same as for an EPROM.
The bus cycle timings can be calculated from the waveforms in Figure 6-7. In the following
example, the timings for
I/O accesses are calculated for CLK2 = 32 MHz and B-series
PALs. All times are in nanoseconds. Check the most recent 80386 Data Sheet to confirm
all parameter values.
tAR: Address stable before Read (MRDC# fall)
tAW: Address stable before Write (MWTC# fall)
(l x CLK2 period) - PAL RegOut Max . - Latch Enable Max
+ PAL RegOut Min
(l x 31.25) - 12 - 11.5
+ 0
= 7.75 nanoseconds
6-11