Intel 80386

MEMORY INTERFACING
tRR: Read (MRDC#) pulse width
(3 x CLK2 period) -
PAL RegOut Max + PAL RegOut Min
(3 x 31.25) - 12 + 0
= 81.75 nanoseconds
tWW: Write (MWTC#) pulse width
(4 x CLK2 period) - PAL RegOut Max+ PAL RegOut Min
(4 x 31.25) -
12 + 0
= 113 nanoseconds
tRA: Address Hold after Read (MRDC# rise)
(0 x CLK2 period)
+ Latch Enable
(0 x 31.25)
- PAL RegOut Max + PAL RegOut Min
- 12
+ 0
+ 5
= -7 nanoseconds (This is acceptable because latched addresses are held for at
least as long as the end of the bus cycle.)
tWA: Address hold after Write (MWTC# rise)
(1 x CLK2 period) - PAL RegOut Max + PAL RegOut Min
+ Latch Enable Min
(1 x 31.25) - 12 + 0
+ 5
= 24.25 nanoseconds
tAD: Data delay from Address
(4 x CLK2 period)
- xcvr. prop. Min
(4 x 31.25)
- 6
= 85.5 nanoseconds
- PAL RegOut Max - Latch Enable Max
- 80386 Data Setup Min
- 12 - 11.5
-10
tRD: Data delay from Read (MRDC#)
(3 x CLK2 period) - PAL RegOut Max - xcvr. prop Min
- 80386 Data Setup Min
(3 x 31.25) - 12 - 6
- 10
= 65.75 nanoseconds
6-13