Intel 80386

CACHE SUBSYSTEMS
31 24 23
2 1 0
32·BIT I CACHE/DRAM
P~~~~~~~R SELECT
TAG I 3- ~~!~LE
1_16 MEGABYTE DRAM ~ 24 BITS ___ I
TAG ~
22 BITS
FFFFFC
000000
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16339C
FFFFF8
'-oo_ ___ ..
2816 BIT SRAM
DATA ~
4 BYTES
24682468
12345678
33333333
87654321
11223344
4096 BIT SRAM
DATA
24682468
11223344
r
33333333
f--
-
87654321
12345678
1-32BITS-i
16 MEGABYTE DRAM
Figure 7-2. Fully Associative Cache Organization.
7.2.2 Direct Mapped Cache
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16339C
163398
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G30107
In a direct mapped cache, unlike a fully associative cache, only one address comparison is
needed to determine whether requested data is in the cache.
The many address comparisons of the fully associative cache are necessary because any
block from the main memory can be placed in any location of the cache. Thus, every block
of the cache must be checked for the requested address. The direct mapped cache reduces
the number of comparisons needed by allowing each block from the main memory only one
possible location in the cache.
Each direct mapped cache address has two parts. The first part, called the cache index field,
contains enough bits to specify a block location within the cache. The second part, called
the tag field, contains enough bits to distinguish a block from other blocks that may be
stored at a particular cache location.
7-4