Intel 80386 - Page 266

DRAM PAL DESCRIPTIONS
FUNCTION TABLE
OE CLK2 CLK CSO CSl CS2 CS3 CS4 A2 RFRQ
ROWSEL Q! QO RASO RAS! MUXOE DRAMSELECT A2REG
;OE
; inputs
;outputs
; I CLK2
; I I CLK ROWSEL
; I I I ICSO I Q!
; I I I I ICS! I I QO
; I I I I I ICS2 I I I IRASO
; I I I I I I CS3 I I I I IRAS!
; I I I I I I I CS4 I I I I I IMUXOE
; I I I I I I I I A2 I I I I I I DRAMSELECT
; I I I I I I I I I RFRQ I I I I I I I A2REG
; I I I I I I I I I I I I I I I I I I STATE
COMMENTS
L·C H H X X X X X L
LCLHXXXXXL
L C H H X X X X X L
L
C L H X X X X X L
L
C H H X X X X X L
L
C L H X X X X X L
L
C H H X X X X X L
LCHHXXXXXL
L C L X X X X X X L
LCHHXXXXXL
LCLXXXXXXL
LCHHXXXXXL
LCLXXXXXXL
L C H L L L H H H L
LCLXXXXXXL
L C H H X X X X X L
LCLXXXXXXL
L C H H X X X X X L
LCLXXXXXXL
LCHHXXXXXL
LCLXXXXXXL
LCHHXXXXXL
LCLXXXXXXL
L C H H X X X X X H
LCLXXXXXXH
L C H L L L H H H H
LCLXXXXXXH
L C H H X X X X X H
LCLHXXXXXL
LCHHXXXXXL
LCLHXXXXXL
L C H H X X X X X L
L C L H X X X X X L
L
C H H X X X X X L
L
C L X X X X X X L
LCHXHXXXXL
L C L X X X X X X L
L
C H X X H X X X L
L
C L X X X X X X L
LCHLLLHHLL
LCLXXXXXXL
LCHXXXLXXL
LCLXXXXXXL
LCHLLLHHXL
LCLXXXXXXL
LCHLLLHHHL
L C L X X X X X X L
LCHXXXLXXL
LCLXXXXXXL
LCHXXXXLXL
L C L X X X X X X L
LCHLLLHHHL
X X X X X X X X; X initialize to IDLE
X X X X X X X X; X initialize to IDLE
X X X X X X X X; X initialize to IDLE
X X X X X X X X; X initialize to IDLE
X X X X X X X X; X initialize to IDLE
X X X X X X X X; X initialize to IDLE
X X X X X X X X; X initialize to IDLE
L L H L H L L L; ACCESS3 continue DRAM cycl e
L H H L H L L L;
ACCESS4 continue DRAM cycle
L H H L H L L L; ACCESS5 continue DRAM cycle
H H L L H L L H; ACCESS6 continue DRAM cycle
H H H H H L L H;PRECHARGE! no dram request pending
H H H H H L L
H;PRECHARGE2 wait for precharge
H L L H L L H
H; ACCESSl start DRAM cycle to other bank
L L L H L L L H; ACCESS2 continue DRAM cycle
L L H H L L L H; ACCESS3 continue DRAM cycle
L H H H L L L H; ACCESS4 continue DRAM cycle
L H H H L L L H; ACCESS5 continue DRAM cycle
H H L H L L L L; ACCESS6 continue DRAM cycle
H H H H H L L L;PRECHARGE! no dram request pending
H H H H H L L
L;PRECHARGE2 wait for precharge
H L H H H L L
X; IDLE! no dram request pending
H L H H H L L
X; IDLE2 wait for precharge
H L H H H L L
X; IDLE! no dram request pending
H L H H H H L
X; IDLE2 refresh request sampled
H L H H H H H H; IDLE! can't start: refresh pending
L H L H H H H
X; REFSTART2 refresh address set-up
H L L L L H H
X; ACCESS! start refresh cycle
X X X X X X X X; X initialize to IDLE
X X X X X X X X; X initialize to IDLE
X X X X X X X X; X initialize to IDLE
X X X X X X X X; X initialize to IDLE
X X X X X X X X; X initialize to IDLE
H L H H H L L X; IDLE! remain in IDLE
H L H H H L L X; IDLE2 remain in IDLE
H L H H H L L X; IDLE! remain in IDLE
H L H H H L L X; IDLE2 remain in IDLE
H L H H H L L X; IDLE! remain in IDLE
H L H H H L L X; IDLE2 remain in IDLE
H L L L H L H L; ACCESS! start DRAM cycle
L L L L H L L L; ACCESS2 continue DRAM cycle
L L H L H L L L; ACCESS3 continue DRAM cycle
L H H L H L L L; ACCESS4 continue DRAM cycle
L H H L H L H L; ACCESS5 continue DRAM cycle new request
H H L L H L H
H; ACCESS6 continue DRAM cycle
H L L H L L H H; ACCESS! start DRAM cycle to other bank
L L L H L L L H; ACCESS2 continue DRAM cycle
L L H H L L L H; ACCESS3 continue DRAM cycle
L H H H L L L H; ACCESS4 continue DRAM cycle
L H H H L L L H; ACCESS5 continue DRAM cycle
H H L H L L L L; ACCESS6 continue DRAM cycle
H H H H H L H L;PRECHARGEl can't start same bank cycle
Figure C-2. 3-CLK DRAM State PAL Equations (Cont'd.)
C-4