Intel 80386 - Page 267

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DESCRIPTION
DRAM PAL DESCRIPTIONS
H H H H H L H L; PRECHARGE2 wa it for precharge
H L H H H L H
X; IDLE! can't start same bank cycle
H L H H H L H X; IDLE2 wait for precharge
H L L H L L H
H; ACCESS! start DRAM cycl e to same bank
L L L H L L L H; ACCESS2 continue DRAM cycle
L L H H L L L H; ACCESS3 continue DRAM cycle
L H H H L L L H; ACCESS4 continue DRAM cycle
L H H H L L H H; ACCESSS continue DRAM cycle new request
H H L H L H H L;
ACCESS6 continue DRAM cycl e refresh req
H H H H H H H L;
PRECHARGE! can't start: refresh pend i ng
H H H H H H H L; PRECHARGE2 wait for precharge
H L H H H H H
X; IDLE! can't start: refresh pending
L H L H H H H
X; REFSTART2 wait for precharge
H L L L L H H
X; ACCESS! start refresh cycle
L L L L L H H X; ACCESS2 continue refresh cycl e
L L H L L H H
X; ACCESS3 continue refresh cycle
L H H L L H H X; ACCESS4 continue refresh cycle
L H H L L H H X; ACCESSS continue refresh cycle
H H L L L H H X; ACCESS6 cant i nue refresh cycle
H H H H H H H X;PRECHARGE! can't start: refresh precharge
H H H H H H H
X; PRECHARGE2 wa i t for precharge
H L H H H H H
X; IDLE! can't start: refresh precharge
H L H H H L H
X; IDLE2 wait for precharge
H L L L H L H L;
ACCESS! start DRAM cycle
L L L L H L L L; ACCESS2 continue DRAM cycl e
*** NOTE - SOME VERSIONS OF PALASM WILL CRASH !F THE FILE IS TOO LONG ***
***
IF YOURS DOES, DELETE THIS DESCRIPTION (FROM HERE TO END-OF-FILE) ***
This PAL implements the main state machine of the DRAM controller.
The state machine is described below.
For
brevity, the following keywords are used
SELECT = (ICSO * ICS! * ICS2 * CS3 * CS4 * CLK)
;chip selects and clock must be active to select
SELECTED = (SELECT + DRAMSELECT) ;true if DRAM is now or has been selected
STARTACCESS = (SELECTED * IMUXOE) ;start dram access cycle from idle
The states are defined below and indicated by [ROWSEL:Q! :QO:CLKj.
The 4- bit bi nary number fo 11 owi ng the state name represents these four signals.
1= ==== = ============ === ===== = = ==== = ====== ======== ===== === \
I state REFSTART2 = 0101 ;cycle preceding refresh I
I IRASO: = ON ; next cycle is fi rst RAS for refresh I
I IRASI:= ON 1---+
I MUXOE:= MUXOE ;maintain MUXOE state I I always
\=====================~~=D=~~~~==~~~~~~~~~~~~~~~~~~~~~ ~~I I
A I
I MUXOE * RFRQ I
I I
I~~~================================================== ==\ I
I state IDLEI = 1010 ;waiting for access or refresh I I
I IRASO:= OFF ;both RAS's idle 1<--1--------+
I IRASI: = OFF I I I
I
MUXOE: = RFRQ ; samp 1 e refresh request I I I
\===================================================== ==1 I I
I A I I
II (MUXOE * RFRQ) I/STARTACCESS I I
v I I I
Figure C-2_ 3-CLK DRAM State PAL Equations (Cont'd.)
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