Intel 80386 - Page 274

DRAM PAL DESCRIPTIONS
Finally. the karnaugh maps for the following signals are:
ROWSEL\QO
Ql\CLK
00 01
11 10
\
MUXOE
00 I
MUX MUX
key:
01 I
MUX MUX
M+R MUX = MUXOE
111
MUX
M+R = MUXOE + RFRQ
10 I
MUX MUX RFR
RFR
= RFRQ
ROWSEL \QO
Ql\CLK
00
01
11
10
\
A2REG
00 I
A2R A2R key:
01 I
A2R A2R A2R A2; = A2
111
A2R
A2R
= A2REG
10 I
A2R A2;
A2;
ROWSEL\QO
Ql\CLK
00
01
11 10
\
RAS signals
00 I lAM AM
lAM AM
key:
[RASO:RASl]
01 I ON ON lAM AM lAM AM AM = A2REG + MUXOE
111
IAI AI AS = A2 * STARTACCESS
10 I lAM AM lAS AS OFFOFF
AI = A2 * STARTACCESS * i nterl eave
ROWSEL \QO
Ql\CLK
00 01
11 10
\
ROWSEL state circled
00 I
OWI0 0111 key: [ROWSEL: Ql: QO: CLK]
01 I
1000 0110
1101 M = MUXOE * RFRQ
111
10iO S = STARTACCESS
10 I
0001
10s0 mMml I = STARTACCESS * interl eave
W = W%R + MUXOE
ROWSEL\QO
Ql\CLK
00 01
11
10
\
Ql state circled
00 I
OWI0
0111
01 I
1000 0110 1101
111
10iO
10 I
0001
10s0
mMml
ROWSEL\QO
Ql\CLK 00 01
11 10
\ QO state circled
10 I
OWI0 0111
111
1000
0110 1101
01 I
10iO
00 I
0001
10s0 mMml
Figure C-3. 2-CLK DRAM State PAL Equations (Cont'd.)
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