DRAM PAL DESCRIPTIONS
DRAM CONTROL PAL
The DRAM Control PAL generates the majority of the control signals for the DRAM circuit.
The inputs sample the W jR# and byte-enable outputs of the 80386 as
well
as
status signals
from the DRAM State PAL. The outputs generate the four CAS signals,
two
transceiver
control signals, and the signals for the 80386 READY # and Next Address (NA#) logic.
Table C-2 contains a description of the outputs and inputs.
The equations for the 3-CLK
DRAM
Control PAL are shown
in
Figure C-4; those for the
2-CLK DRAM Control PAL are shown
in
Figure C-5. A 16R8 PAL
is
needed to register
the CAS signals internally. A 16R4 PAL
is
needed when external registers drive the CAS
signals. For a 16-MHz system, B-series PAL speeds are required.
REFRESH INTERVAL COUNTER PAL
The Refresh Interval Counter PAL, which periodically generates refresh requests to the
DRAM
State PAL, operates as a counter decremented every CLK cycle. Once the counter
reaches a preset value, it resets its value to
255
and activates its
RFRQ
(refresh request)
output. This output remains active until both REFACK (refresh acknowledge) inputs are
sampled simultaneously active.
Setup and hold times for
RFRQ
to the DRAM State PAL are guaranteed
even
with a large
CLK2-to-CLK skew because the Refresh Interval Counter PAL
is
clocked
by
the rising edge
of
CLK, and the
RFRQ
output
is
only sampled by the DRAM State PAL at the middle-of-
phase CLK2 edge. However, the CLK2-to-CLK and output delays can add up
so
that the
setup and hold times for the
REF
ACK inputs are not met. Therefore, the REF ACK inputs
are activated for a minimum of four CLK2 periods to ensure deactivation of RFRQ. The
exact CLK
in
which
RFRQ
is
deactivated
is
not critical.
Table C-3 shows the inputs and outputs of the Refresh Interval Counter PAL. Figure C-6
shows its PAL equations. The same equations are used for both the 3-CLK and 2-CLK
designs. A 20XlO PAL
is
used to implement this counter. For 16-MHz systems, A-series
PAL
speeds are sufficient.
REFRESH ADDRESS COUNTER PAL
The Refresh Address Counter PAL maintains the address of the next DRAM row to be
refreshed. After every refresh cycle, the PAL increments this address. Table C-4 shows the
inputs and outputs of the Refresh Address Counter PAL.
PAL
equations are shown
in
Figure C-7. Both the 3-CLK and the 2-CLK design use the
same equations. Most DRAMs require only 8-bits or fewer for the refresh
row
address,
so
a
16R8
PAL
can be used.
If
necessary,
10
bits of row address can be provided using a 20XlO
PAL. For a system operating at any speed, standard-PAL speeds are sufficient.
C-13
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