Intel 80386 - Page 286

DRAM PAL DESCRIPTIONS
FUNCTION TABLE
OE CLOCK
A7 A6 AS A4 A3 A2 Al AO
,
;OE
; I CLOCK
;1 I
A7
I A6
I I AS
I I I A4
II II A3
I I I I I A2
I I I I I I Al
I II II II AO
11111111
COMMENTS
; inputs
;outputs
L C H H H H H H H H; initialize (ignore any errors on this vector)
L C L L L L L L L L; increment
L
C L L L L L L L H; increment
L
C L L L L L L H L; increment
L
C L L L L L L H H; increment
L
C L L L L L H L L; increment
H H
Z Z Z Z Z Z Z Z; high-impedence state
DESCRIPTION
This PAL implements a simple 8-bit counter which is used to
generate the refresh row address by the DRAM controller.
Figure C-7. Refresh Address Counter PAL Equations (Cont'd.)
C-24