Intel 80386

LOCAL BUS INTERFACE
During the HOLD state, the 80386 can continue executing instructions in its Prefetch Queue.
Program execution
is delayed if a read cycle is needed while the 80386 is in the HOLD
state. The 80386 can queue one write cycle internally, pending the return of bus access; if
more than one write cycle
is needed, program execution is delayed until HOLD is released
and the
80386 regains control of the bus.
HOLD has priority over most bus cycles, but HOLD is not recognized between two interrupt
acknowledge cycles, between
two repeated cycles of a BS16 cycle, or during locked cycles.
For the 80386,
HOLD is recognized between two cycles required for misaligned data trans-
fers; for the
8086 and 80286 HOLD it is not recognized. This difference should be consid-
ered if critical misaligned data transfers are not locked.
HOLD is not recognized while RESET is active, but is recognized during the time between
the high-to-Iow transition of
RESET and the first instruction fetch.
All inputs are ignored while the
80386 is in the HOLD state, except for the following:
• HOLD is monitored to determine when the 80386 may regain control of the bus.
• RESET takes precedence over the HOLD state. An active RESET input will reinitialize
the 80386.
• One NMI request is recognized and latched. It is serviced after HOLD is released.
3.6.2 HOLD Signal Latency
Because other bus masters such
as DMA controllers are typically used in time-critical appli-
cations, the amount of time the bus master must wait (latency) for bus access can be a
critical design consideration.
The minimum possible latency occurs when the
80386 receives the HOLD input during an
idle cycle. HLDA
is asserted on the CLK2 rising edge following the HOLD active input
(synchronous to CLK2).
Because a bus cycle must be terminated before HLDA can
go active, the maximum possible
latency occurs when a bus-cycle instruction
is being executed. Wait states increase latency,
and
HOLD is not recognized between locked bus cycles, repeated cycles due to BS16#, and
interrupt acknowledge cycles.
3.6.3 HOLD State Pin Conditions
LOCK#,
M/IO#, DIC#, W IR#, ADS#, A31-A2, BE3#-BEO#, and D31-DO enter the three-
state
OFF condition in the HOLD state. Note that external pullup resistors may be required
on ADS#, LOCK# and other signals to guarantee that they remain inactive during transi-
tions between bus masters.
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