Intel 80386

inter
COPROCESSOR HARDWARE INTERFACE
o Status Enable (STEN) serves as a chip select for the 80387. This pin is high to enable
the 80387, and may be driven low to float all 80387 outputs. STEN may be used to do
onboard testing (using the overdrive method). STEN may also be used to activate one
80387 at a time, in systems with multiple 80387s. If not needed, STEN should be pulled
high.
• Ready Out (READYO#) can be used to acknowledge 80387 bus cycles. The 80387
activates READYO# at such a time that write cycles are terminated after two clocks and
read cycles are terminated after three clocks. READYO# can be connected to the 80386
READY # input through logic that ORs READY # signals from other devices. Alterna-
tively, READYO# can be left disconnected, and external logic can be used to acknowl-
edge 80387 bus cycles.
5.2.2 80387 Bus Cycles
When the 80386 encounters a coprocessor instruction, it automatically generates one or more
I/O cycles to addresses 800000F8H and 800000FCH. The 80386 will perform all necessary
bus cycles to memory and transfer data to and from the 80387. All 80387 transfers are
32 bits wide. If the memory subsystem is only 16 bits wide, the 80386 automatically performs
the necessary conversion before transferring data to or from the 80387. Since the 80387 is
a 32-bit device, BSI6# must not be asserted during 80387 communication cycles.
Read cycles (transfers from the 80387 to the 80386) require at least one wait state, whereas
write cycles to the 80387 require no wait states. This requirement is automatically reflected
in the state of the READYO# output of the 80387, which can be used to generate the
necessary wait state.
5.2.3 80387 Clock Input
The 80387 can be operated in two modes. In either mode, the CLIO signal must be connected
to the 386CLK2 input of the 80387 because the interface to the 80386 is always synchron-
ous. The state of the 80387 CKM input determines its mode:
o In synchronous mode, CKM is high and the 387CLK2 input is not connected. The 80387
operates from the CLK2 signal. Operation of the 80387 is fully synchronous with that of
the 80386.
• In pseudo-synchronous mode, CKM is low and a frequency source for the 387CLK2 input
must be provided. Only the interface logic of the 80387 is synchronous with the 80386.
The internal logic of the 80387 operates from the 387CLK2 clock source, whose frequency
may be 10/16 to 16/10 times the speed of CLK2. Figure 5-3 depicts pseudo-
synchronous operation.
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