MEMORY INTERFACING
oPALs
are inexpensive compared to dedicated bus controllers.
o Once a
PAL
design has been tested, Hard Array Logic
(HAL)
devices, which are mask-
programmed
PALs, can be used
in
production quantities (several thousand units).
PALs also have the following disadvantages:
o Pin counts or speeds of available PALs can restrict some designs.
o Most PALs do not have buried (not connected to outputs) state registers; therefore,
in
state-machine implementations, registered output pins must be used to store the current
state.
o The drive capability of PALs may be insufficient for some applications.
In
these cases,
buffering
is
required.
A
PAL
device consists logically of a programmable
AND
array whose output terms feed a
fixed
OR
array. Any sum-of-products equation, within the limits of the number of
PAL
inputs, outputs, and equation terms, can be realized
by
specifying the correct
AND
array
connections. Figure 6-2 shows an example of two
PAL equations and the corresponding logic
array. Note
that
every horizontal line in the
AND
array represents a multi-input
AND
gate;
every vertical line represents a possible input to the
AND
gate. The X at the intersection of
a horizontal line and a vertical line represents a connection from the input to the
AND
gate.
Programming a
PAL
device consists of determining where the
XS
must
be
placed in the
AND
array. This task
is
simplified by the use of a
PAL
assembler program. Such a program
accepts input in the form of sum-of-products equations. The assembled code
is
then applied
to a
PAL
device using a standard
PROM
programmer equipped with a special
PAL
enhancement.
The following conventions apply to
TTL
and PAL devices described in this section:
o
TTL
devices are specified by number (function), but not by family (speed). Virtually any
family of a device can be used if it meets the performance requirements of the applica-
tion. For example, a
74xOO
device might be implemented with a
74FOO
or
74ASOO.
Generally, the F and AS families provide the highest performance.
o
PAL
devices are specified by
part
number. A
PAL
part number generally consists of a
number, a letter, and a second number, and
is
interpreted
as
shown in Figure 6-3. PALs
are manufactured for a number of performance levels. Standard PALs are suitable unless
otherwise specified.
6.2.2
Address Latch
Latches maintain the address for the duration of the bus cycle and are necessary to pipeline
addresses because the address for the next bus cycle appears
on
the address lines before the
current cycle ends.
In
this example, 74x373 latches are used. Although the 80386 can be
run without address pipelining to eliminate the need for address latching, the system will
usually run less efficiently.
6-3
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