Intel 8086 User Manual

8086
WAVEFORMS (Continued)
ASYNCHRONOUS SIGNAL RECOGNITION
231455–17
NOTE:
1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK.
BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
231455–18
RESET TIMING
231455–19
REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
231455–20
NOTE:
The coprocessor may not drive the buses outside the region shown without risking contention.
24

Intel 8086 Specifications

General

Architecture	x86
Clock Speed	5 MHz to 10 MHz
Data Width	16-bit
Address Bus Width	20-bit
Transistor Count	29, 000
Instruction Set	x86
Package	40-pin DIP
Microarchitecture	8086
Addressable Memory	1 MB
Manufacturing Process	3 μm
Voltage	+5V
Introduced	1978
Registers	14 registers (including segment registers)