Specification Update 29
BV30. Spurious Interrupts May be Generated From the Intel® VT-d Remap
Engine
Problem: If software clears the F (Fault) bit 127 of the Fault Recording Register (FRCD_REG at
offset 0x208 in Remap Engine BAR) by writing 1b through RW1C command (Read Write
1 to Clear) when the F bit is already clear then a spurious interrupt from Intel VT-d
(Virtualization Technology for Directed I/O) Remap Engine may be observed.
Implication: Due to this erratum, spurious interrupts will occur from the Intel VT-d Remap Engine
following RW1C clearing F bit.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BV31. Malformed PCIe Transactions May be Treated as Unsupported
Requests Instead of as Critical Errors
Problem: PCIe MSG/MSG_D TLPs (Transaction Layer Packets) with incorrect Routing Code as well
as the deprecated TCfgRD and TCfgWr types should be treated as malformed
transactions leading to a critical error. Due to this erratum, the integrated PCIe
controller's root ports may treat such messages as UR (Unsupported Requests).
Implication: Legacy malformed PCIe transactions may be treated as UR instead of as critical errors.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BV32. Reception of Certain Malformed Transactions May Cause PCIe Port to
Hang Rather Than Reporting an Error
Problem: If the processor receives an upstream malformed non posted packet for which the type
field is IO, Configuration or the deprecated TCfgRd and the format is 4 DW header, then
due to this erratum the integrated PCIe controller may hang instead of reporting the
malformed packet error or issuing an unsupported request completion transaction.
Implication: Due to this erratum, the processor may hang without reporting errors when receiving a
malformed PCIe transaction. Intel has not observed this erratum with any commercially
available device.
Workaround: None identified. Upstream transaction initiators should avoid issuing unsupported
requests with 4 DW header formats.
Status: For the steppings affected, see the Summary Tables of Changes.
BV33. Clock Modulation Duty Cycle Cannot be Programmed to 6.25%
Problem: When programming field T_STATE_REQ of the IA32_CLOCK_MODULATION MSR (19AH)
bits [3:0] to '0001, the actual clock modulation duty cycle will be 12.5% instead of the
expected 6.25% ratio.
Implication: Due to this erratum, it is not possible to program the clock modulation to a 6.25% duty
cycle.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
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