Intel Cyclone 10 GX FPGA - Page 16

Bank Number Function I/O Type I/O Count Description
1C/1D
PCIE_RX [0:3]
CML/LVDS input 8(4p) PCIe Gen2 Receive
1D
SFP+_TX [0:1]
CML output 4(2p) SFP+ Transmit
1D
SFP+_RX [0:1]
CML / LVDS input 4(2p) SFP+ Receive
1D
USB31_TX
CML output 2(1p) USB3.1 Trasnsmit
1D
USB31_RX
CML/LVDS input 2(1p) USB3.1 Receive
1C/1D
FMC_DP_C2M [0:4]
CML output 10(5p) FMC Transmit
1C/1D
FMC_DP_M2C [0:4]
CML/LVDS input 10(5p) FMC Receive
Global FPGA Clocks
2A
M10_USB_CLK
1.8 V CMOS input 1 30/48 MHz from U2
(MAX10)
2A
C10_REFCLK1
LVDS input 2 125 MHz (adjustable)
2L
C10_CLK50M
1.8 V CMOS input 1 50 MHz OSC, free
running
2L
C10_REFCLK2
LVCMOS input 2 100 MHz (adjustable)
2J
REFCLK_EMIF
LVDS input 2 21.186 MHz
(adjustable)
Global FPGA Reset
2A
FPGA_RESETn
1.8 V CMOS input 1 From U2 (Intel MAX
10)
JTAG
CSS
C10_TCK
1.8 V CMOS input 1 From U2 (Intel MAX
10)
CSS
C10_TMS
1.8V CMOS input 1 From U2 (Intel MAX
10)
CSS
C10_TDI
1.8 V CMOS input 1 From U2 (Intel MAX
10)
CSS
C10_TDO
1.8 V CMOS input 1 To U2 (Intel MAX 10)
Configuration
2A
C10_CLKUSR
1.8 V CMOS input 1 100 MHz, for
calibration
CSS
C10_MSEL[0:1]
1.8 V CMOS input 2 From DIP Switch S1
CSS
C10_nSTATUS
1.8 V CMOS output 1 To U2/U3 (Intel MAX
10)
CSS
C10_CONF_DONE
1.8 V CMOS output 1 To U2/U3 (Intel MAX
10)
CSS
C10_nCONFIG
1.8 V CMOS input 1 From U2 (Intel MAX
10)
CSS
C10_CS0n
1.8 V CMOS output 1 To U4 (EPCQ-L)
CSS
C10_AS_D [0:3]
1.8 V CMOS inout 4 To U4 (EPCQ-L)
CSS
C10_DCLK
1.8 V CMOS inout 1 To U4 (EPCQ-L) for
ASx4
continued...
4 Development Board Components
UG-20105 | 2017.12.18
Intel
®
Cyclone
®
10 GX FPGA Development Kit User Guide
16