Intel Cyclone 10 GX FPGA - Page 17

Bank Number Function I/O Type I/O Count Description
From U3 (Intel MAX
10)
for FPPx16
2A
FPP [0:15]
1.8 V CMOS input 16 From U3 (Intel MAX
10)
2A
CVP_CONFDONE
1.8 V CMOS output 1 To U2 (Intel MAX 10)
UBII Side Bus
2A
M10_USB_DATA
[0:7]
1.8 V CMOS input 8 From U2 (Intel MAX
10)
2A
M10_USB_ADDR
[0:1]
1.8 V CMOS input 2 From U2 (Intel MAX
10)
2A
M10_USB_RDn
1.8 V CMOS input 1 From U2 (Intel MAX
10)
2A
M10_USB_WRn
1.8 V CMOS input 1 From U2 (Intel MAX
10)
2A
M10_USB_RESETn
1.8 V CMOS input 1 From U2 (Intel MAX
10)
2A
M10_USB_FULL
1.8 V CMOS output 1 From U2 (Intel MAX
10)
2A
M10_USB_EMPTY
1.8 V CMOS output 1 From U2 (Intel MAX
10)
2A
M10_USB_Oen
1.8 V CMOS input 1 From U2 (Intel MAX
10)
2A
M10_USB_SCL
1.8 V CMOS input 1 From U2 (Intel MAX
10)
2A
M10_USB_SDA
1.8 V CMOS inout 1 From U2 (Intel MAX
10)
EMIF
2J
DDR3_A [0:14]
1.5 V SSTL output 15 To U12/U13/U14
DDR3
2J
DDR3_BA [0:2]
1.5 V SSTL output 3 To U12/U13/U14
DDR3
2J
DDR3_RASn
1.5 V SSTL output 1 To U12/U13/U14
DDR3
2J
DDR3_CASn
1.5 V SSTL output 1 To U12/U13/U14
DDR3
2J
DDR3_WEn
1.5 V SSTL output 1 To U12/U13/U14
DDR3
2J
DDR3_CK
1.5 V SSTL output 2 To U12/U13/U14
DDR3
2J
DDR3_CKE [0:1]
1.5 V SSTL output 2 To U12/U13/U14
DDR3
2J
DDR3_ODT [0:1]
1.5 V SSTL output 2 To U12/U13/U14
DDR3
2J
DDR3_CS [0:1]
1.5 V SSTL output 2 To U12/U13/U14
DDR3
continued...
4 Development Board Components
UG-20105 | 2017.12.18
Intel
®
Cyclone
®
10 GX FPGA Development Kit User Guide
17