Intel Cyclone 10 GX FPGA - Page 18

Bank Number Function I/O Type I/O Count Description
2J
DDR3_RSTn
1.5 V CMOS output 1 To U12/U13/U14
DDR3
2J/2K
DDR3_D [0:39]
1.5 V SSTL inout 40 To U12/U13/U14
DDR3
2J/2K
DDR3_DQS [0:4]
1.5 V SSTL inout 10 To U12/U13/U14
DDR3
FMC LVDS GPIO
3A/3B
FMC_LA_TX [0:16]
Vadj CMOS inout 34 To J7 (FMC), DC
3A/3B
FMC_LA_RX [0:14]
Vadj CMOS inout 30 To J7 (FMC), DC
3A/3B
FMC_LA_CC [0:1]
Vadj CMOS input 4 From J7 (FMC), DC
3A/3B
FMCA_CLK_M2C
[0:1]
Vadj CMOS input 4 From J7 (FMC), DC
3B
FMC_PRSN_1V8
Vadj CMOS input 1 From J7 (FMC)
3A
FMC_SCL
Vadj CMOS output 1 To J7 (FMC)
3A
FMC_SDA
Vadj CMOS inout 1 To J7 (FMC)
10/100/1000 Base-T
2A
SGMII_TXP/N
LVDS output 2 To U33 (88E1111
PHY), AC
2A
SGMII_TXP/N
LVDS input 2 To U33 (88E1111
PHY), AC
2L
ETH_MDC_C10
1.8 V CMOS output 1 To U33 (88E1111 PHY)
2L
ETH_MDIO_C10
1.8 V CMOS inout 1 To U33 (88E1111
PHY), AC
2L
ETH_INTn_C10
1.8 V CMOS input 1 To U33 (88E1111
PHY), AC
2L
ETH_RESETn_C10
1.8 V CMOS output 1 To U33 (88E1111
PHY), AC
SFP+ sideband
2L
SFP_SCL_0
1.8 V CMOS output 1 To J5 (SFP+ 0)
2L
SFP_SDA_0
1.8 V CMOS inout 1 To J5 (SFP+ 0)
2L
SFP_INT_0
1.8 V CMOS input 1 To J5 (SFP+ 0)
2L
SFP_SCL_1
1.8 V CMOS output 1 To J6 (SFP+ 1)
2L
SFP_SDA_1
1.8 V CMOS inout 1 To J6 (SFP+ 1)
2L
SFP_INT_1
1.8 V CMOS input 1 To J6 (SFP+ 1)
PCIe sideband
2L
PCIE_WAKEn
1.8 V CMOS input 1 To golden finger,
reserved
2L
PCIE_SMBCLK
1.8 V CMOS output 1 To golden finger
2L
PCIE_SMBDAT
1.8 V CMOS inout 1 To golden finger
2A
PCIE_PERSTn
1.8 V CMOS input 1 To golden finger
continued...
4 Development Board Components
UG-20105 | 2017.12.18
Intel
®
Cyclone
®
10 GX FPGA Development Kit User Guide
18