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Intel Cyclone 10 GX FPGA - Page 52

Intel Cyclone 10 GX FPGA
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Port
Allows you to specify the interface to test. The following port are available to test:
XCVR
CMOS
PMA Settings
Allows you to make changes to the PMA parameters that affect the active transceiver
interface. The following settings are available for analysis:
Serial Loopback: Routes signals between the transmitter and receiver.
VOD: Specifies the voltage output differential of the transmitter buffer.
Pre-emphasis tap:
1st pre - Specifies the amount of pre-emphasis on the pre-tap of the
transmitter buffer.
2nd pre - Specifies the amount of pre-emphasis on the second pre-tap of the
transmitter buffer.
1st post - Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
2nd post - Specifies the amount of pre-emphasis on the second post tap of the
transmitter buffer.
Equalizer: Specifies the AC gain setting for the receiver equalizer in four stage
mode.
DC gain: Specifies the DC gain setting for the receiver equalizer in four stage
mode.
VGA: Specifies the VGA gain value.
Figure 17. PMA Settings
Data Type
Specifies the type of data contained in the transactions. The following data types are
available for analysis.
5 Board Test System
UG-20105 | 2017.12.18
Intel
®
Cyclone
®
10 GX FPGA Development Kit User Guide
52

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